Datasheet

229
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
21.3 DDRSDRC Module Diagram
Figure 21-1. DDRSDRC Module Diagram
DDRSDRC is partitioned in two blocks (see Figure 21-1):
 An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and
integrates an arbiter.
 A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
Memory Controller
Finite State Machine
SDRAM Signal Management
Addr, DQM
Data
Asynchronous Timing
Refresh Management
DDR-SDR
Devices
Power Management
DQS
RAS, CAS,
WE, CKE
CLK/NCLK
ODT
DDR-SDR Controller
Interconnect Matrix
Input
Stage
Input
Stage
Input
Stage
Output
Stage
Arbiter
APB
A
HB Slave Interface 0
AHB Slave Interface 1
AHB Slave Interface 2
AHB Slave Interface 3
Input
Stage
Interface APB