Datasheet

215
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Figure 20-32. Clock Rate Transition Occurs While the SMC is Performing a Write Operation
Figure 20-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
A
[25:2]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
111 2
3
2
NWE_CYCLE = 7
NORMAL MODE WRITE
Slow clock mode transition is detected:
Reload Configuration Wait State
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
SLOW CLOCK MODE WRITE
NBS0, NBS1,
NBS2, NBS3,
A0,A1
A [25:2]
NCS
1
MCK
NWE
1
1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
2
3
2
NORMAL MODE WRITEIDLE STATE
Reload Configuration
Wait State
NBS0, NBS1,
NBS2, NBS3,
A0,A1