Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
202
 in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback
of the write control signal is used to control address, data, chip select and byte select lines. If the external
write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is
inserted and address, data and control signals are maintained one more cycle. See Figure 20-19.
Figure 20-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup
Figure 20-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
write cycle
Early Read
wait state
MCK
NRD
NWE
read cycle
no setup
no hold
D[31:0]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A[25:2]
write cycle
(WRITE_MODE = 0)
Early Read
wait state
MCK
NRD
NCS
read cycle
(READ_MODE = 0 or READ_MODE = 1)
no setup
no hold
D[31:0]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
A[25:2]