Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
200
20.8.5 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according
to their type.
The SMC_SETUP register groups the definition of all setup parameters:
 NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
 NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
 NRD_CYCLE, NWE_CYCLE
Table 20-4 shows how the timing parameters are coded and their permitted range.
20.8.6 Reset Values of Timing Parameters
Table 20-8 gives the default value of timing parameters at reset.
20.8.7 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE
parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold
values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews
between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines,
and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State”
on page 201.
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable
behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
Table 20-4. Coding and Range of Timing Parameters
Coded Value Number of Bits Effective Value
Permitted Range
Coded Value Effective Value
setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ 31 0 ≤ 128 + 31
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ 63 0 ≤ 256 + 63
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ 127
0 ≤ 256 + 127
0 ≤ 512 + 127
0 ≤ 768 + 127