Datasheet

19
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
 Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the
ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926
Data Master and by the AHB Masters through the AHB bus.
 Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is
performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB
Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by
the ARM926 Instruction and the ARM926 Data Masters.
Within the 64 Kbytes SRAM size available, the amount of memory assigned to each block is software
programmable according to Table 5-1.
5.2.3 Internal ROM
The SAM9G45 embeds an Internal ROM, which contains the boot ROM and SAM-BA
®
program.
At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the
reset and before the Remap Command.
Table 5-1. TCM and DTCM Memory Configuration
SRAM A ITCM size (Kbytes) seen at
0x100000 through AHB
SRAM B DTCM size (Kbytes) seen at
0x200000 through AHB
SRAM C (Kbytes) seen at
0x300000 through AHB
0064
0640
32 32 0