Datasheet

175
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits
A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash
device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the
device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even
when NCSx is not selected, preventing the device from returning to standby mode.
Figure 19-10. NAND Flash Application Example
D[7:0]
ALE
NANDWE
NANDOE
NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO
R/B
EBI
CE
NAND Flash
PIO
NCSx/NANDCS
Not Connected