Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
174
19.2.7.7 NAND Flash Support
External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.
External Bus Interface
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI_CS3A field in the CCFG_EBICSA register to the appropriate value enables the NAND Flash logic. For details
on this register, refer to Section 18. “Bus Matrix (MATRIX)”. Access to an external NAND Flash device is then
made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address
fails to lie in the NCS3 address space. See Figure 19-10 for more information. For details on these waveforms,
refer to Section 20. “Static Memory Controller (SMC)”.
Figure 19-9. NAND Flash Signal Multiplexing on EBI Pins
SMC
NRD_NOE
NWR0_NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx
NANDWE
NANDOE