Datasheet

169
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
19.2.6 Product Dependencies
19.2.6.1 I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O
lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO
Controller.
19.2.7 Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses
and is composed of the following elements:
 The Static Memory Controller (SMC)
 The DDR2/SDRAM Controller (DDRSDRC)
 The ECC Controller (ECC)
 A chip select assignment feature that assigns an AHB address space to the external devices
 A multiplex controller circuit that shares the pins between the different Memory Controllers
 Programmable CompactFlash support logic
 Programmable NAND Flash support logic
19.2.7.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits
and the control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines
at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float
times defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed
independently by the DDR SDR SDRAM Controller (DDRSDRC) without delaying the other external Memory
Controller accesses.
19.2.7.2 Pull-up Control
The EBI Chip Select Assignment Register (CCFG_EBICSA) in Section 18.7.6 “Chip Configuration User Interface”
permit enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The
pull-up resistors are enabled after reset. Setting the CCFG_EBICSA.EBI_DBPUC bit disables the pull-up resistors
on the lines D0–D15. Enabling the pull-up resistor on the lines D16–D31 can be performed by programming the
appropriate PIO controller.
19.2.7.3 Static Memory Controller
For information on the Static Memory Controller, refer to Section 20. “Static Memory Controller (SMC)”.
19.2.7.4 DDR2SDRAM Controller
For information on the DDR2SDRAM Controller, refer to Section 21. “DDR SDR SDRAM Controller (DDRSDRC)”.
19.2.7.5 ECC Controller
For information on the ECC Controller, refer to Section 22. “Error Correction Code Controller (ECC)”.
19.2.7.6 CompactFlash Support
The External Bus Interface 0 integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address
space. Programming the EBI_CS4A and/or EBI_CS5A bit of the CCFG_EBICSA register to the appropriate value
enables this logic. (For details on this register, refer to the Section 18. “Bus Matrix (MATRIX)”.) Access to an