Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
166
19.2.5 Application Example
19.2.5.1 Hardware Interface
Table 19-4 details the connections to be applied between the EBI pins and the external devices for each Memory
Controller.
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1, 2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. BEx: Byte x Enable (x = 0, 1, 2 or 3)
Table 19-4. EBI Pins and External Static Devices Connections
Signals: EBI_
Pins of the SMC Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
4 x 8-bit
Static
Devices
2 x 16-bit
Static
Devices
32-bit Static
Device
D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7
D8–D15 – D8–D15 D8–D15 D8–D15 D8–15 D8–15
D16–D23 – – – D16–D23 D16–D23 D16–D23
D24–D31 – – – D24–D31 D24–D31 D24–D31
A0/NBS0 A0 – NLB – NLB
(3)
BE0
(5)
A1/NWR2/NBS2 A1 A0 A0 WE
(2)
NLB
(4)
BE2
(5)
A2–A25 A[2:25] A[1:24] A[1:24] A[0:23] A[0:23] A[0:23]
NCS0 CS CS CS CS CS CS
NCS1/DDRSDCS CS CS CS CS CS CS
NCS2 CS CS CS CS CS CS
NCS3/NANDCS CS CS CS CS CS CS
NCS4/CFCS0 CS CS CS CS CS CS
NCS5/CFCS1 CS CS CS CS CS CS
NRD/CFOE OE OE OE OE OE OE
NWR0/NWE WE WE
(1)
WE WE
(2)
WE WE
NWR1/NBS1 – WE
(1)
NUB WE
(2)
NUB
(3)
BE1
(5)
NWR3/NBS3 – – – WE
(2)
NUB
(4)
BE3
(5)