Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
164
19.2.3 EBI Block Diagram
Figure 19-4. Organization of the External Bus Interface
External Bus Interface
D[15:0]
A[15:2], A18
PIO
MUX
Logic
User Interface
Chip Select
Assignor
Static
Memory
Controller
DDR2
LPDDR
SDRAM
Controller
Bus Matrix
APB
AHB
Address Decoders
A16/BA0
A0/NBS0
A1/NWR2/NBS2
A17/BA1
NCS0
NRD/CFOE
NCS1/SDCS
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCK#, SDCKE
DQM[1:0]
DQS[1:0]
RAS, CAS
SDWE
D[31:16]
A[24:19]
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
NCS2
CFCE1
CFCE2
NWAIT
SDA10
NANDOE
NANDWE
NAND Flash
Logic
CompactFlash
Logic
ECC
Controller
A21/NANDALE
A22/NANDCLE
NCS3/NANDCS
DQM[3:2]