Datasheet

163
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
19.2.2.3 DDR2/SDR Controller
 Supports DDR/LPDDR, SDR-SDRAM and LPSDR
 Numerous Configurations Supported
 2K, 4K, 8K, 16K Row Address Memory Parts
 SDRAM with Four Internal Banks
 SDR-SDRAM with 16- or 32- bit Data Path
 DDR2/LPDDR with 16-bit Data Path
 One Chip Select for SDRAM Device (256 Mbyte Address Space)
 Programming Facilities
 Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of
Transactions)
 Timing Parameters Specified by Software
 Automatic Refresh Operation, Refresh Rate is Programmable
 Automatic Update of DS, TCR and PASR Parameters (LPSDR)
 Energy-saving Capabilities
 Self-refresh, Power-down and Deep Power Modes Supported
 SDRAM Power-up Initialization by Software
 CAS Latency of 2, 3 Supported
 Auto Precharge Command Not Used
 SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
 Clock Frequency Change in Precharge Power-down Mode Not Supported
19.2.2.4 NAND Flash Error Correction Code Controller
 Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
 Single bit error correction and 2-bit Random detection.
 Automatic Hamming Code Calculation while writing
 ECC value available in a register
 Automatic Hamming Code Calculation while reading
 Error Report, including error flag, correctable error flag and word address being detected erroneous
 Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages