Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
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19.1.4 I/O Lines Description
19.1.5 Product Dependencies
The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines.
Table 19-1. DDR2 I/O Lines Description
Name Function Type Active Level
DDR2/LPDDR Controller
DDR_D0–DDR_D15 Data Bus I/O
DDR_A0–DDR_A13 Address Bus Output
DDR_DQM0–DDR_DQM1 Data Mask Output
DDR_DQS0–DDR_DQS1 Data Strobe Output
DDR_VREF Reference Voltage for DDR2 operations, typically 0.9V Input
DDR_CS Chip Select Output Low
DDR_CLK - #DDR_CLK DDR2 Differential Clock Output
DDR_CKE Clock enable Output High
DDR_RAS Row signal Output Low
DDR_CAS Column signal Output Low
DDR_WE Write enable Output Low
DDR_BA0–DDR_BA1 Bank Select Output