Datasheet

159
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
19.1.3 DDR2 Controller Block Diagram
Figure 19-2. Organization of the DDR2
DDR2
User Interface
Bus Matrix
APB
AHB
Address Decoders
DDR2
LPDDR
Controller
DDR_A0-DDR_A13
DDR_D0-DDR_D15
DDR_CS
DDR_CKE
DDR_RAS, DDR_CAS
DDR_CLK,#DDR_CLK
DDR_DQS[0..1]
DDR_DQM[0..1]
DDR_WE
DDR_BA0, DDR_BA1
DDR_VREF