Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
158
19.1 DDRSDRC0 Multi-port DDRSDR Controller
19.1.1 Description
The DDR2 Controller is dedicated to 4-port DDR2/LPDDR support. Data transfers are performed through a 16-bit
data bus on one chip select. The DDR2 Controller operates with 1.8V Power Supply (VDDIOM0).
19.1.2 Embedded Characteristics
19.1.2.1 DDR2/LPDDR Controller
Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction
Latency.
 Supports AHB Transfers:
 Word, Half Word, Byte Access.
 Supports DDR-SDRAM 2, LPDDR
 Numerous Configurations Supported
 2K, 4K, 8K, 16K Row Address Memory Parts
 DDR2 with Four Internal Banks
 DDR2/LPDDR with 16-bit Data Path
 One Chip Select for DDR2/LPDDR Device (256 Mbytes Address Space)
 Programming Facilities
 Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of
Transactions)
 Timing Parameters Specified by Software
 Automatic Refresh Operation, Refresh Rate is Programmable
 Automatic Update of DS, TCR and PASR Parameters
 Energy-saving Capabilities
 Self-refresh, Power-down and Deep Power Modes Supported
 Power-up Initialization by Software
 CAS Latency of 2, 3 Supported
 Reset function supported (DDR2)
 Auto Precharge Command Not Used
 On Die Termination not supported
 OCD mode not supported