Datasheet

15
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
4.2.1 Power-up Sequence
Figure 4-1. VDDCORE and VDDIO Constraints at Startup
V
DDCORE
and V
DDBU
are controlled by the internal PORs (Power-on Reset) to guarantee that these power sources
reach their target values prior to the release of POR.
 V
DDIOP
must be ≥ V
IH
(refer to Table 45-2 “DC Characteristics” for more details) within (t
RST
+t
1
) after
V
DDCORE
has reached V
T+
 V
DDIOM
must reach V
OH
(refer to Table 45-2 “DC Characteristics” for more details) within (t
RST
+ t
1
+ t
2
) after
V
DDCORE
has reached V
T+
 t
RST
is a POR characteristic
 t
1
= 3 × t
SLCK
 t
2
= 16 × t
SLCK
The t
SLCK
min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz).
 t
RST
= 30 µs
 t
1
= 66 µs
 t
2
= 352 µs
In conclusion, V
DDIOP
and V
DDIOM
must be established first, then V
DDCORE
to ensure a reliable operation of the
device. V
DDOSC
, V
DDPLL
, V
DDUTMII
and V
DDUTMIC
must be started at any time prior to V
DDCORE
to ensure correct
behavior of the ROM code.
V
DD
(V)
Core Supply POR Output
V
DDIO
typ
V
IH
V
T+
t
SLCK
<---- t
RST
--->
V
DDIO
> V
IH
V
DDCORE
V
DDIO
<- t
1
->
V
DDCORE
typ
V
OH
V
DDIO
> V
OH
<------------ t
2
----------->