Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
136
Table 18-5 summarizes the Slave Memory Mapping for each connected Master, depending on the Remap status
(RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and the BMS state at reset.
Table 18-3. Masters to Slaves Access DDRMP_DIS = 0
Master 0 1 2 3 4 & 5 6 7 8 9 10 11
Slave
ARM
926 Instr.
ARM
926 Data PDC
USB Host
OHCI DMA
ISI
DMA
LCD
DMA
Ethernet
MAC
USB
Device HS
USB Host
EHCI Reserved
0 Internal SRAM 0 X X X X X X - X X X -
1
Internal ROM X X X - - - - - X - -
UHP OHCI X X - - - - - - - - -
UHP EHCI X X - - - - - - - - -
LCD User Int. X X - - - - - - - - -
UDPHS RAM X X - - - - - - - - -
Reserved X X - - - - - - - - -
2 DDR Port 0 X - - - - - - - - - -
3 DDR Port 1 - X - - - - - - - - -
4 DDR Port 2 - - - - - - - - - - X
5 DDR Port 3 - - X X X X X X X X -
6 EBI X X X X X X X X X X X
7 Internal Peripheral X X X - X - - - - - -
Table 18-4. Masters to Slaves Access with DDRMP_DIS = 1 (default)
Master 01234 & 567891011
Slave
ARM
926 Instr.
ARM
926 Data PDC
USB
HOST
OHCI DMA
ISI
DMA
LCD
DMA
Ethernet
MAC
USB
Device HS
USB Host
EHCI Reserved
0Internal SRAM 0XXXXXX -XXX -
1
Internal ROMXXX-----X--
UHP OHCIXX---------
UHP EHCIXX---------
LCD User Int.XX---------
UDPHS RAMXX---------
Reserved XX---------
2 DDR Port 0 ----------X
3 DDR Port 1 ------X----
4 DDR Port 2 X - - - -------
5 DDR Port 3 - XXXXX - XXX-
6 EBI XXXXXXXXXXX
7 Internal Peripheral X X X - X ------