Datasheet

135
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
18.2.3 Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing
access from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and
shown as “-” in the following tables.
The four DDR ports are connected differently according to the application device.
The user can disable the DDR multi-port in the DDR Multi-port Register (bit DDRMP_DIS) in the Chip
Configuration User Interface.
 When the DDR multi-port is enabled (DDRMP_DIS = 0), the ARM instruction and data are respectively
connected to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2 and DDR Port 3.
 When the DDR multi-port is disabled (DDRMP_DIS = 1), DDR Port 1 is dedicated to the LCD controller. The
remaining masters share DDR Port 2 and DDR Port 3.
Figure 18-1. DDR Multi-port
LCD
DMA
ARM D
DDRMP_DIS
DDR_S1
DDR_S2
DDR_S3
ARM D
ARM I
MATRIX