Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
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18.2.1 Matrix Masters
The Bus Matrix of the SAM9G45 manages Masters, thus each master can perform an access concurrently with
others, depending on whether the slave it accesses is available.
Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the
addressing, all the masters have the same decodings.
18.2.2 Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 18-1. List of Bus Matrix Masters
Master 0 ARM926
™
Instruction
Master 1 ARM926 Data
Master 2 Peripheral DMA Controller (PDC)
Master 3 USB HOST OHCI
Master 4 DMA
Master 5 DMA
Master 6 ISI Controller DMA
Master 7 LCD DMA
Master 8 Ethernet MAC DMA
Master 9 USB Device High Speed DMA
Master 10 USB Host High Speed EHCI DMA
Master 11 Reserved
Table 18-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
Reserved
Slave 2 DDR Port 0
Slave 3 DDR Port 1
Slave 4 DDR Port 2
Slave 5 DDR Port 3
Slave 6 External Bus Interface
Slave 7 Internal Peripherals