Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1214
Errata
- “Boot ROM” errata added.
- “Static Memory Controller (SMC)” errata added.
- “Touch Screen (TSADCC)” errata added.
- “USB High Speed Host Port (UHPHS)” errata added.
- 3 “Error Corrected Code Controller (ECC)” errata added: “ECC: Uncomplete parity status when error in
ECC parity” , “ECC: Unsupported ECC per 512 words” and “ECC: Unsupported hardware ECC on 16-bit
Nand Flash”
7148
6977
7165
7194
7192
External Memories
- DQM0-3 added to Figure 20-4 “EBI Connections to Memory Devices”.
- Table 20-5, row ‘A15’ edited.
- Section 20.2.7.7 “NAND Flash Support” edited.
- Section 20. “External Memories” reorganized.
- On Figure 6-1 “SAM9G45 Memory Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and ‘DDR2-
LPDDR’ --> ‘DDRSDRC20’.
- All ‘DDR2SDRC’ changed into ‘DDRSDRC’.
7123
7027
6924
6946
Mechanical Characteristics
- New Figure 47-1 “324-ball TFBGA Package Drawing” and Max. weight changed in Table 47-2
- All ‘nominal’ changed into ‘typical’.
- An empty square after letter ‘V’ removed from the Section 49.1 “SAM9G45 Errata - Rev. A Parts” table.
6954
rfo
(1)
PMC
- Note added to Section 26.4 “Master Clock Controller” and Section 26.12.12 “PMC Master Clock
Register”.
7106
USART
- LIN Mode condition now shown in Section 33. “Universal Synchronous Asynchronous Receiver
Transmitter (USART)”.
6944
Doc. Rev
6438E Comments
Change
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Ref.
Introduction:
“Two Three-channel 32-bit Timer/Counters” peripheral feature changed into “Two Three-channel 16-bit
Timer/Counters” .
6828
ECC row added to Figure 6-1 “SAM9G45 Memory Mapping” 6842
Typos corrected in Table 8-1: AC97 --> AC97C (also in Table 24-1 and Table 41-1), PWMC --> PWM,
RNG --> TRNG (also in Figure 2-1 and Table 46-4)
rfo
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Bus Matrix (MATRIX):
Figure 19-1 “DDR Multi-port”, and text above and below added.
1 row and 1 column added to Table 19-3 and Table 19-4.
6797
Doc. Rev
6438F Comments (Continued)
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Ref.