Datasheet

1207
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
04-Dec-15
Section 21. “DDR SDR SDRAM Controller (DDRSDRC)”
Section 21.4.2 “Low-power DDR1-SDRAM Initialization”: step 8 split into step 8 and new step 9; replaced step 12 with
standard text
Figure 21-12 “Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Device”: in diagram, inserted additional
cycle (“Latency = 2” corrected to “Latency = 3”)
Section 22. “Error Correction Code Controller (ECC)”
Table 22-1 “Register Mapping”:
- removed reset value from ECC_CR (register is write-only)
- defined offset range 0x14–0xFC as reserved
Section 23. “Peripheral DMA Controller (PDC)”
Table 23-2 “Register Mapping”: removed reset value from PERIPH_PTCR (register is write-only)
Section 25. “Power Management Controller (PMC)”
Section 25.9 “Programmable Clock Output Controller”: in first sentence, “controls PMC_PROG_CLK_NB signals”
corrected to “controls two signals”
Section 25.10 “Programming Sequence”: in step 5, “PMC_PROG_CLK_NB programmable clocks” corrected to “two
programmable clocks”
Table 25-2 “Register Mapping”:
- “UTMI Clock Register” corrected to “UTMI Clock Configuration Register”
- access for PMC_PLLICPR changed from “Write-only” to “Read/Write”
Section 25.12.18 “PLL Charge Pump Current Register”: access changed from “Write-only” to “Read/Write”
Section 26. “Advanced Interrupt Controller (AIC)”
Removed reset value from register description sections (reset values provided in Table 26-3 “Register Mapping”)
Section 30. “Two-wire Interface (TWI)”
Table 30-6 “Register Mapping”: removed reset value from TWI_THR (register is write-only)
Removed reset value from register description sections (reset values provided in Table 30-6 “Register Mapping”)
Section 32. “Universal Synchronous Asynchronous Receiver Transmitter (USART)”
Table 32-8 “Possible Values for the Fi/Di Ratio”: in top row, “774” corrected to “744”
Table 32-13 “IrDA Baud Rate Error”: in header row, added “bit/s” to Baud Rate and added “µs” to Pulse Time
Section 32.7.8.7 “Slave Node Synchronization”: in list of parameters, instance of “OVER = 0 => 8X” corrected to
“OVER = 1 => 8X”
Table 32-17 “Register Mapping”: added reset value 0x0 to US_MR, US_CSR, US_NER
Removed reset value from Section 32.8.12 “USART FI DI RATIO Register” (reset values provided in Table 32-17
“Register Mapping”)
Section 33. “Synchronous Serial Controller (SSC)”
Section 33.7.1.1 “Clock Divider”: at end of section, deleted untitled Table 33-2
Section 35. “High Speed Multimedia Card Interface (HSMCI)”
Updated Section 35.2 “Embedded Characteristics”
Section 35.8.1 “Command - Response Operation”: updated text and Figure 35-7 “Command/Response Functional Flow
Diagram” with “busy indication” and “NOTBUSY” flag
Added Section 35.13 “Write Protection Registers”
Table 35-8 “Register Mapping”: defined offset range 0x100–0x1FC as reserved; offset range for FIFO Memory Aperture
registers updated to 0x200–0x5FC
Section 35.14.2 “HSMCI Mode Register”: added sentence about disabling write protection
Table 50-2. SAM9G45 Datasheet Rev. 6438N Revision History (Continued)
Date Changes