Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1206
Table 50-2. SAM9G45 Datasheet Rev. 6438N Revision History
Date Changes
04-Dec-15
General formatting and editorial changes throughout
Updated “Description”
“Features”
Updated descriptions under “Peripherals”, “System”, and “Package”; added “Cryptography”
Section 1. “Block Diagram”
Figure 1-1 “SAM9G45 Block Diagram”: added label “Backup Section”
Section 2. “Signal Description”
Table 2-1 “Signal Description List”:
- “DDR Memory Interface- DDR2/SDRAM/LPDDR Controller” renamed to “DDR Memory Interface - DDR2/LPDDR
Controller - DDRSDRC0”
- “DDR2/SDRAM/LPDDR Controller” renamed to “EBI - DDR2/SDRAM/LPDDR Controller - DDRSDRC1”
Section 4. “Power Considerations”
Updated Section 4.1 “Power Supplies”
Added Section 4.2 “Power Sequence Requirements” (transferred from Section 45.12 “Core Power Supply POR
Characteristics”)
Section 5. “Memories”
Section 5.2.2 “TCM Interface”: in first sentence, “can be allocated to two areas” corrected to “can be allocated to three
areas”
Section 5.3.1 “I/O Drive Selection”: “EBI_CSA register” corrected to “CCFG_EBICSA register”
Section 7. “Peripherals”
Section 7.4 “Peripheral Signals Multiplexing on I/O Lines”: below last paragraph, deleted sentence “To amend EMC,
programmable delay has been inserted on PIO lines able to run at high speed”
Section 8. “ARM926EJ-S Processor Overview”
Section 8.4.10 “Thumb Instruction Set Overview”: deleted sentence “Table 5 shows the Thumb instruction set, for further
details, see the ARM Technical Reference Manual”
Section 10. “Boot Strategies”
Deleted sentence “For optimization purpose, nothing else is done.”
Section 10.5.3.2 “USB class”: removed reference to “Windows XP”
Section 13. “Real-time Clock (RTC)”
Section 13.2 “Embedded Characteristics”: deleted bullet “Control of alarm and update Time/Calendar Data In”
Section 18. “Bus Matrix (MATRIX)”
Removed reset value from register description sections in Section 18.7.6 “Chip Configuration User Interface” (reset values
provided in Table 18-7 “Register Mapping (Chip Configuration User Interface)”)
Section 19. “External Memories”
Table 19-4 “EBI Pins and External Static Devices Connections”:
- added footnote to pins BE0–BE3
- in last two rows, changed two instances of “NLB” to “NUB”
Section “CFCE1 and CFCE2 Signals”: updated content describing DBW field configuration
Added Figure 19-9 “NAND Flash Signal Multiplexing on EBI Pins”