Datasheet

1205
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
50. Revision History
In the tables that follow, the most recent version appears first.
Table 50-1. SAM9G45 Datasheet Rev. 6438O Revision History
Date Changes
08-Dec-15
Minor formatting and editorial changes throughout
Section 13. “Real-time Clock (RTC)”
Table 13-1 “Register Mapping”: defined offset 0xFC as “Reserved”
Section 27. “Debug Unit (DBGU)”
Table 27-3 “Register Mapping”: defined offset range 0x004C–0x00FC as “Reserved”
Section 28. “Serial Peripheral Interface (SPI)”
Section 28.3 “Block Diagram”: inserted Figure 28-1 “Block Diagram” (shows implementation of PDC)
Added Figure 28-9 “PDC Status Register Flags Behavior” and associated introductory text
Added Section 28.7.3.6 “SPI Peripheral DMA Controller (PDC)”
Added Section 28.7.3.7 “Transfer Size”
Added Section 28.7.3.10 “Peripheral Deselection Without PDC nor DMAC”
Added Section 28.7.3.11 “Peripheral Deselection with PDC”
Table 28-5 “Register Mapping”:
- defined offset range 0x004C–0x00FC as “Reserved”
- defined offset range 0x100–0x124 as “Reserved for the PDC”
Section 28.8.5 “SPI Status Register”: removed UNDES bit
Section 28.8.6 “SPI Interrupt Enable Register”: removed UNDES bit
Section 28.8.7 “SPI Interrupt Disable Register”: removed UNDES bit
Section 28.8.8 “SPI Interrupt Mask Register”: removed UNDES bit
Section 39. “Touchscreen ADC Controller (TSADCC)”
Table 39-4 “Register Mapping”: defined offset range 0x64–0xE0 as “Reserved”