Datasheet

1185
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Notes: 1. For output signals, Min and Max access time must be extracted. The Min access time is the time between the SPCK rising
or falling edge and the signal change. The Max access time is the time between the SPCK rising or falling edge and the
signal stabilization. Figure 45-11 illustrates Min and Max accesses for SPI
2
. The same applies to SPI
5
, SPI
6
, and SPI
9
.
Table 45-47. USART SPI Timings with 3.3V Peripheral Supply
Symbol Parameter Conditions Min Max Unit
SPI
0
SPCK Period
Master Mode
––ns
SPI
1
Input Data Setup Time 17.2 – ns
SPI
2
Input Data Hold Time 0 – ns
SPI
3
Chip Select Active to Serial Clock – 3.5 ns
SPI
4
Output Data Setup Time – 0.2 ns
SPI
5
Serial Clock to Chip Select Inactive – -0.3 ns
SPI
6
SPCK falling to MISO
Slave Mode
13.8
(1)
16.9
(1)
ns
SPI
7
MOSI Setup time before SPCK rises 7.5 – ns
SPI
8
MOSI Hold time after SPCK rises 2.9 – ns
SPI
9
SPCK rising to MISO 4.7
(1)
17.1
(1)
ns
SPI
10
MOSI Setup time before SPCK falls 0.4 – ns
SPI
11
MOSI Hold time after SPCK falls 0 – ns
SPI
12
NPCS0 setup to SPCK rising 10.3 – ns
SPI
13
NPCS0 hold after SPCK falling 2.0 – ns
SPI
14
NPCS0 setup to SPCK falling 10.7 – ns
SPI
15
NPCS0 hold after SPCK rising 2.0 – ns
SPI
16
NPCS0 falling to MISO valid – 16.0 ns