Datasheet

1181
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
45.15.5 EMAC
45.15.5.1 Timing Conditions
Timings are given assuming a capacitance load on data and clock as defined in Table 45-42.
45.15.5.2 Timing Constraints
The Ethernet controller satisfies the timings of the standards given in Table 45-43, Table 45-44 and Table 45-45.
Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EMDC falling
edge and the signal change. The Max access time is the time between the EMDC falling edge and the signal stabilization.
Figure 45-22 illustrates Min and Max accesses for EMAC3.
Figure 45-22. Min and Max Access Time of EMAC Output Signals
45.15.5.3 MII Mode
Table 45-42. Capacitance Load on Data, Clock Pads
Supply
Corner
Max Min
3.3V 20 pF 0 pF
1.8V 20 pF 0 pF
Table 45-43. EMAC Signals Relative to EMDC
Symbol Parameter Min Max Unit
EMAC
1
Setup for EMDIO from EMDC rising 13.5 – ns
EMAC
2
Hold for EMDIO from EMDC rising 10 – ns
EMAC
3
EMDIO toggling from EMDC falling 0
(1)
2
(1)
ns
EMDC
EMDIO
EMAC
3 max
EMAC
1
EMAC
2
EMAC
4
EMAC
5
EMAC
3 min
Table 45-44. EMAC MII Specific Signals
Symbol Parameter Min Max Unit
EMAC
4
Setup for ECOL from ETXCK rising 10 – ns
EMAC
5
Hold for ECOL from ETXCK rising 10 – ns
EMAC
6
Setup for ECRS from ETXCK rising 10 – ns
EMAC
7
Hold for ECRS from ETXCK rising 10 – ns
EMAC
8
ETXER toggling from ETXCK rising 3 25 ns
EMAC
9
ETXEN toggling from ETXCK rising 4.7 25 ns
EMAC
10
ETX toggling from ETXCK rising 3 25 ns
EMAC
11
Setup for ERX from ERXCK 10 – ns
EMAC
12
Hold for ERX from ERXCK 10 – ns