Datasheet

1171
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
45.14 DDRSDRC Timings
The DDRSDRC controller satisfies the timings of standard DDR2, LPDDR, SDR and LPSDR modules.
DDR2, LPDDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
 DDR2-400 limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK/CK#)
 LPDDR (1.8V, 30 pF on data/control, 10 pF on CK)
 t
a
= 5.0 ns, f
max
= 125 MHz
 t
a
= 6.0 ns, f
max
= 110 MHz
 t
a
= 7.5 ns, f
max
= 95 MHz
 SDR-100 (3.3V, 50 pF on data/control, 10 pF on CK)
 SDR-133 (3.3V, 50 pF on data/control, 10 pF on CK)
 LPSDR-133 (1.8V, 30 pF on data/control, 10 pF on CK)
45.15 Peripheral Timings
45.15.1 SPI
45.15.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write
modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI
2
(or
SPI
5
) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 45.9 “I/Os”),
the max SPI frequency is the one from the pad.
Master Read Mode
t
valid
is the slave time response to output data after deleting an SPCK edge. For a non-volatile memory with t
valid
(or
t
v
) = 12 ns Max, f
SPCK
Max = 38.5 MHz @ V
DDIO
= 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold
timings SPI
7
/SPI
8
(or SPI
10
/SPI
11
). Since this gives a frequency well above the pad limit, the limit in slave
read mode is given by SPCK pad.
Slave Write Mode
For 3.3V I/O domain and SPI6, f
SPCK
Max = 33 MHz. t
setup
is the setup time from the master before sampling
data.
f
SPCK
Max
1
SPI
0
or SPI
3
()t
valid
+
----------------------------------------------------------
=
f
SPCK
Max
1
SPI
6
or SPI
9
()t
setup
+
------------------------------------------------------------
=