Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1166
45.11 Touchscreen ADC (TSADC)
Note: 1. The Track and Hold Acquisition Time is given by:
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion
time is give by:
The full speed is obtained for an input source impedance of < 50 ohms maximum, or TTH = 500 ns.
To achieve optimal performance of the TSADC, the SHTIM field in TSADCC Mode Register is to be calculated according to
this Track and Hold Acquisition Time, also called Sampled and Hold Time.
Table 45-21. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Unit
ADC Clock Frequency 10-bit resolution mode – – 13.2 MHz
Startup Time Return from Idle Mode – – 40 µs
Track and Hold Acquisition Time (TTH) ADC Clock = 13.2 MHz
(1)
0.5 – – µs
Conversion Time (TCT) ADC Clock = 13.2 MHz
(1)
– – 1.75 µs
Throughput Rate ADC Clock = 13.2 MHz
(1)
– – 440 ksps
Table 45-22. External Voltage Reference Input
Parameter Conditions Min Typ Max Unit
TSADVREF Input Voltage Range – 2.4 – V
DDANA
V
TSADVREF Average Current – – – 600 µA
Current Consumption on VDDANA – – – 300 µA
Table 45-23. Analog Inputs
Parameter Min Typ Max Unit
Input Voltage Range 0 – ADVREF V
Input Leakage Current – – 1 µA
Input Capacitance – 7 10 pF
Input Source Impedance – 50 – Ω
Table 45-24. Transfer Characteristics
Symbol Parameter Min Typ Max Unit
Resolution – 10 – bit
INL Integral Non-linearity – – ±2 LSB
DNL Differential Non-linearity -0.9 – +0.9 LSB
E
O
Offset Error -1.5 0.5 ±10 mV
E
G
Gain Error – – ±2 LSB
TTH (ns) 500 0.12 Z
IN
×()Ω()+=
TCT µs()
23
f
clk
--------
MHz()=