Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1164
The following configuration of fields PMC_PLLICPR.ICPLLA and CKGR_PLLAR.OUTA must be done for each
PLLA frequency range.
45.8.1 UTMI PLL Characteristics
45.9 I/Os
Criteria used to define the maximum frequency of the I/Os:
 Output duty cycle (40%–60%)
 Minimum output swing: 100 mV to VDDIO - 100 mV
 Addition of rising and falling time inferior to 75% of the period
Notes: 1. V
DDIOP
from 3.0V to 3.6V
2. V
DDIOP
from 1.65V to 1.95V
Table 45-15. PLLA Frequency Configuration
PLL Frequency Range (MHz) PMC_PLLICPR.ICPLLA CKGR_PLLAR.OUTA
745–800 0 00
695–750 0 01
645–700 0 10
595–650 0 11
545–600 1 00
495–550 1 01
445–500 1 10
400–450 1 11
Table 45-16. Phase Lock Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
IN
Input Frequency – 4 12 32 MHz
f
OUT
Output Frequency – 450 480 600 MHz
I
PLL
Current Consumption
Active mode – 5 8 mA
Standby mode – – 1.5 µA
t
START
Startup Time – – – 50 µs
Table 45-17. I/O Characteristics
Symbol Parameter Conditions Min Max Unit
f
max
VDDIOP-powered pins frequency
3.3V domain
(1)
Max. external load = 20 pF
Max. external load = 40 pF
–
66
34
MHz
1.8V domain
(2)
Max. external load = 20 pF
Max. external load = 40 pF
–
35
18