Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1106
Figure 44-5. STN Panel Timing, CLKMOD 0
Figure 44-6. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
LCDHSYNC
LCDVSYNC
LCDDEN
LCDDOTCK
LCDD
Frame Period
VHDLY+ HBP+1HPW+1
HFP+VHDLY+2 HOZVAL+1
LCDDOTCK
LCDD
1 PCLK
1/2 PCLK 1/2 PCLK
Line Period
LCDVSYNC
LCDHSYNC
LCDDEN
VHDLY+1 HBP+1 HPW+1
HFP+VHDLY+2
HOZVAL+1
LCDDOTCK
LCDD
1 PCLK
1/2 PCLK
1/2 PCLK
Line Period
LCDVSYNC
LCDHSYNC
LCDDEN
(VPW+1) Lines
LCDVSYNC
LCDDOTCK
LCDD
LCDDEN
VHDLY+1
LCDHSYNC
Vertical Fron t Porch = VFP Lines
Vertical Back Porch = VBP Lines
Frame Period