Datasheet

1105
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be
displayed on the panel.
The following timing parameters can be configured:
 Vertical to Horizontal Delay (VHDLY): The delay between the falling edge of LCDVSYNC and the generation
of LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to (VHDLY+1)
LCDDOTCK cycles.
 Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of LCDTIM2
register. The width is equal to (HPW + 1) LCDDOTCK cycles.
 Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first LCDDOTCK
rising edge with valid data at the LCD Interface is configurable in the HBP field of the LCDTIM2 register. The
delay is equal to (HBP+1) LCDDOTCK cycles.
 Horizontal Front Porch (HFP): The delay between end of valid data and the generation of the next
LCDHSYNC is configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+VHDLY+2)
LCDDOTCK cycles.
There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by the initial latency of
the datapath. The total delay in LCDC clock cycles must be higher than or equal to the latency column in Table 44-
4 on page 1098. This limitation is given by the following formula:
Equation 1
where:
 VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers
 PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles
 DPATH_LATENCY is the datapath latency of the configuration, given in Table 44-4 on page 1098
The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at
the top of the display. The timing of this signal depends on the type of LCD: STN or TFT LCD.
In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode, this signal is
synchronized with the first active LCDDOTCK rising edge in a line.
In TFT mode, the high phase of this signal starts at the beginning of the first line. The following timing parameters
can be selected:
 Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register.
The pulse width is equal to (VPW+1) lines.
 Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of
LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in
STN Mode.
 Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of
LCDTIM2 register. The number of inactive lines is equal to VFP. This field should be programmed with 0 in
STN mode.
There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the
LCDFRMCFG:
 HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in
each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.
 LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The
minimum value of this parameter is 1.
Figure 44-5, Figure 44-6 and Figure 44-7 show the timing of LCDDOTCK, LCDDEN, LCDHSYNC and LCDVSYNC
signals:
VHDLY HPW HBP 3+++()PCLK_PERIOD× DPATH_LATENCY≥