Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1104
Figure 44-3. Full Frame Timing, MMODE = 1, MVAL = 1
Figure 44-4. Full Frame Timing, MMODE = 0
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through
LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL
field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BYPASS bit in
the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The
minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in Table
44-14.
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2
register:
 Always Active (used with TFT LCD Modules)
 Active only when data is available (used with STN LCD Modules)
The LCDDEN signal indicates valid data in the LCD Interface.
Table 44-14. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
Configuration
LCDDOTCK PeriodDISTYPE SCAN IFWIDTH
TFT 1
STN Mono Single 4 4
STN Mono Single 8 8
STN Mono Dual 8 8
STN Mono Dual 16 16
STN Color Single 4 2
STN Color Single 8 2
STN Color Dual 8 4
STN Color Dual 16 6
LCDVSYNC
LCDMOD
LCDDOTCK
Line1 Line2 Line3 Line4 Line5
LCDVSYNC
LCDMOD
LCDDOTCK
Line1 Line2 Line3 Line4 Line5
f
LCDDOTCK
f
LCDC_clock
CLKVAL 1+
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