Datasheet

1103
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Note: Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF.
gi = green pixel component OFF. bi = blue pixel component OFF.
44.6.2.7 Shifter
The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three
sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output
interface. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LDCCON3
register.
The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCANMODE field selects
between single and dual scan modes; in TFT mode, only single scan is supported. The IFWIDTH field configures
the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only).
For a more detailed description of the fields, see “LCD Controller (LCDC) User Interface” on page 1118.
For a more detailed description of the LCD Interface, see “LCD Interface” on page 1108.
44.6.2.8 Time Generator
The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, and
LCDMOD, used by the LCD module. This block is programmable in order to support different types of LCD
modules and obtain the output clock signals, which are derived from the LCDC Core clock.
The LCDMOD signal provides an AC signal for the display. It is used by the LCD to alternate the polarity of the row
and column voltages used to turn the pixels on and off. This prevents the liquid crystal from degradation. It can be
configured to toggle every frame (bit MMODE = 0 in LCDMVAL register) or to toggle every programmable number
of LCDHSYNC pulses (bit MMODE = 1, number of pulses defined in MVAL field of LCDMVAL register).
Figure 44-3 and Figure 44-4 show the timing of LCDMOD in both configurations.
N+1 red_data_1 1010 0 1011 LCDD[0] LCDD[4] R1
N+1 green_data_1 1010 3 1011 LCDD[3] LCDD[3] G1
N+1 blue_data_1 1010 2 1011 LCDD[2] LCDD[2] b1
…… … … … … ……
N+2 red_data_0 1010 3 0110 LCDD[3] LCDD[7] r0
N+2 green_data_0 1010 2 0110 LCDD[2] LCDD[6] G0
N+2 blue_data_0 1010 1 0110 LCDD[1] LCDD[5] B0
N+2 red_data_1 1010 0 0110 LCDD[0] LCDD[4] r1
N+2 green_data_1 1010 3 0110 LCDD[3] LCDD[3] g1
N+2 blue_data_1 1010 2 0110 LCDD[2] LCDD[2] B1
…… … … … … ……
Table 44-13. Dithering Algorithm for Color Mode (Continued)
Frame Signal Shadow Level Bit used Dithering Pattern 4-bit LCDD 8-bit LCDD Output
f
LCD_MOD
f
LCD_HSYNC
2 MVAL 1+()×
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