Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1102
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The
dithering pattern for the first pair member is the inversion of the one for the second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)
th
bit of the pattern determines if a pixel with
horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current
frame. The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. The
four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is DP3_5 =”1010 0101 1010
0101 1111”.
The output sequence obtained in the data output for monochrome mode is shown in Table 44-12.
Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. A
color pixel is composed of three components: {R, G, B}. Pixel p0 will be displayed sending the color components
{R0, G0, B0} to the display. Pixel p1 will be displayed sending the color components {R1, G1, B1}. Suppose that
the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color
components of both pixels, with the dithering pattern to apply to all of them being DP2_3 = “1101 1011 0110”.
Table 44-13 shows the output sequence in the data output bus for single scan configurations. (In Dual Scan
Configuration, each panel data bus acts like in the equivalent single scan configuration.)
Table 44-12. Dithering Algorithm for Monochrome Mode
Frame Number Pattern Pixel a Pixel b Pixel c Pixel d
N 1010 ON OFF ON OFF
N+1 0101 OFF ON OFF ON
N+2 1010 ON OFF ON OFF
N+3 0101 OFF ON OFF ON
N+4 1111 ON ON ON ON
N+5 1010 ON OFF ON OFF
N+6 0101 OFF ON OFF ON
N+7 1010 ON OFF ON OFF
... ... ... ... ... ...
Table 44-13. Dithering Algorithm for Color Mode
Frame Signal Shadow Level Bit used Dithering Pattern 4-bit LCDD 8-bit LCDD Output
N red_data_0 1010 3 1101 LCDD[3] LCDD[7] R0
N green_data_0 1010 2 1101 LCDD[2] LCDD[6] G0
N blue_data_0 1010 1 1101 LCDD[1] LCDD[5] b0
N red_data_1 1010 0 1101 LCDD[0] LCDD[4] R1
N green_data_1 1010 3 1101 LCDD[3] LCDD[3] G1
N blue_data_1 1010 2 1101 LCDD[2] LCDD[2] B1
…… … … … … ……
N+1 red_data_0 1010 3 1011 LCDD[3] LCDD[7] R0
N+1 green_data_0 1010 2 1011 LCDD[2] LCDD[6] g0
N+1 blue_data_0 1010 1 1011 LCDD[1] LCDD[5] B0