Datasheet

1101
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
For the structure of each LUT entry, see Table 44-10.
In STN Monochrome, only the four most significant bits of the red value are used (16 gray shades). In STN Color,
only the four most significant bits of the blue, green and red value are used (4096 colors).
In TFT mode, all the bits in the blue, green and red values are used. The LCDD unused bits are tied to 0 when TFT
palettized configurations are used (LCDD[18:16], LCDD[9:8], LCDD[2:0]).
44.6.2.6 Dithering
The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN
LCD Module. It uses a time-based dithering algorithm and Frame Rate Control method.
The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the display an
appearance of multiple shades. In order to reduce the flicker noise caused by turning on and off adjacent pixels at
the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. This
algorithm is expressed in terms of Dithering Pattern registers (DP_i) and considers not only the pixel gray level
number, but also its horizontal coordinate.
Table 44-11 shows the correspondences between the gray levels and the duty cycle.
Table 44-10. Lookup Table Structure in the Memory
Address Data Output [15:0]
00 Red_value_0[4:0] Green_value_0[5:0] Blue_value_0[4:0]
01 Red_value_1[4:0] Green_value_1[5:0] Blue_value_1[4:0]
...
FE Red_value_254[4:0] Green_value_254[5:0] Blue_value_254[4:0]
FF Red_value_255[4:0] Green_value_255[5:0] Blue_value_255[4:0]
Table 44-11. Dithering Duty Cycle
Gray Level Duty Cycle Pattern Register
15 1 –
14 6/7 DP6_7
13 4/5 DP4_5
12 3/4 DP3_4
11 5/7 DP5_7
10 2/3 DP2_3
9 3/5 DP3_5
8 4/7 DP4_7
71/2~DP1_2
63/7~DP4_7
52/5~DP3_5
41/3~DP2_3
31/4~DP3_4
21/5~DP4_5
11/7~DP6_7
00–