Datasheet

1095
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
44.5.3 Interrupt Sources
The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller.
Using the LCD Controller interrupt requires prior programming of the AIC.
44.6 Functional Description
The LCD Controller consists of two main blocks (Figure 44-1 on page 1092), the DMA controller and the LCD
controller core (LCDC core). The DMA controller reads the display data from an external memory through a AHB
master interface. The LCD controller core formats the display data. The LCD controller core continuously pumps
the pixel data into the LCD module via the LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK,
LCDDEN, LCDHSYNC, and LCDVSYNC signals.
44.6.1 DMA Controller
44.6.1.1 Configuration Block
The configuration block is a set of programmable registers that are used to configure the DMA controller operation.
These registers are written via the AHB slave interface. Only word access is allowed.
For details on the configuration registers, see “LCD Controller (LCDC) User Interface” on page 1118.
44.6.1.2 AHB Interface
This block generates the AHB transactions. It generates undefined-length incrementing bursts as well as 4-, 8- or
16-beat incrementing bursts. The size of the transfer can be configured in the BRSTLN field of the DMAFRMCFG
register. For details on this register, see “DMA Frame Configuration Register” on page 1126.
44.6.1.3 Channel-U
This block stores the base address and the number of words transferred for this channel (frame in single scan
mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame
signal.
It has two pointers, the base address and the number of words to transfer. When the module receives a
new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. When the
module receives the new_frame signal, it also reloads the base address with the base address programmed by the
host.
The size of the frame/panel can be programmed in the FRMSIZE field of the DMAFRMCFG Register. This size is
calculated as follows:
where:
X_size = ((LINESIZE+1)*Bpp+PIXELOFF)/32
Y_size = (LINEVAL+1)
 LINESIZE is the horizontal size of the display in pixels, minus 1, as programmed in the LINESIZE field of the
LCDFRMCFG register of the LCD Controller.
 Bpp is the number of bits per pixel configured.
 PIXELOFF is the pixel offset for 2D addressing, as programmed in the DMA2DCFG register. Applicable only
if 2D addressing is being used.
Table 44-3. Peripheral IDs
Instance ID
LCDC 23
Frame_size
X_size*Y_size
32
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