Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
1094
44.5.2 Power Management
The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the Power
Management Controller before using it (PMC_PCER).
LCDC LCDD10 PE13 B
LCDC LCDD10 PE17 A
LCDC LCDD11 PE14 B
LCDC LCDD11 PE18 A
LCDC LCDD12 PE15 B
LCDC LCDD12 PE19 A
LCDC LCDD13 PE16 B
LCDC LCDD13 PE20 A
LCDC LCDD14 PE17 B
LCDC LCDD14 PE21 A
LCDC LCDD15 PE18 B
LCDC LCDD15 PE22 A
LCDC LCDD16 PE23 A
LCDC LCDD17 PE24 A
LCDC LCDD18 PE19 B
LCDC LCDD18 PE25 A
LCDC LCDD19 PE20 B
LCDC LCDD19 PE26 A
LCDC LCDD20 PE21 B
LCDC LCDD20 PE27 A
LCDC LCDD21 PE22 B
LCDC LCDD21 PE28 A
LCDC LCDD22 PE23 B
LCDC LCDD22 PE29 A
LCDC LCDD23 PE24 B
LCDC LCDD23 PE30 A
LCDC LCDHSYNC PE4 A
LCDC LCDMOD PE1 A
LCDC LCDPWR PE0 A
LCDC LCDVSYNC PE3 A
Table 44-2. I/O Lines (Continued)
Instance Signal I/O Line Peripheral