Datasheet

1051
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
42.6 Product Dependencies
42.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the AC97 Controller receiver, the PIO controller must be configured in order for the AC97C receiver
I/O lines to be in AC97 Controller peripheral mode.
Before using the AC97 Controller transmitter, the PIO controller must be configured in order for the AC97C
transmitter I/O lines to be in AC97 Controller peripheral mode.
42.6.2 Power Management
The AC97 Controller is not continuously clocked. Its interface may be clocked through the Power Management
Controller (PMC), therefore the programmer must first configure the PMC to enable the AC97 Controller clock.
The AC97 Controller has two clock domains. The first one is supplied by PMC and is equal to MCK. The second
one is AC97CK which is sent by the AC97 Codec (Bit clock).
Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be higher than the
AC97CK (Bit Clock) clock frequency.
42.6.3 Interrupt
The AC97 Controller interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling
interrupts requires programming the AIC before configuring the AC97C.
All AC97 Controller interrupts can be enabled/disabled by writing to the AC97 Controller Interrupt Enable/Disable
Registers. Each pending and unmasked AC97 Controller interrupt will assert the interrupt line. The AC97
Controller interrupt service routine can get the interrupt source in two steps:
 Reading and ANDing AC97 Controller Interrupt Mask Register (AC97C_IMR) and AC97 Controller Status
Register (AC97C_SR).
 Reading AC97 Controller Channel x Status Register (AC97C_CxSR).
Table 42-2. I/O Lines
Instance Signal I/O Line Peripheral
AC97C AC97CK PD9 A
AC97C AC97FS PD8 A
AC97C AC97RX PD6 A
AC97C AC97TX PD7 A
Table 42-3. Peripheral IDs
Instance ID
AC97C 24