Datasheet

1027
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This
implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true
when the PWM master clock is turned off through the Power Management Controller.
41.6.2 PWM Channel
41.6.2.1 Block Diagram
Figure 41-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
 A clock selector which selects one of the clocks provided by the clock generator described in Section 41.6.1
“PWM Clock Generator” on page 1026.
 An internal counter clocked by the output of the clock selector. This internal counter is incremented or
decremented according to the channel configuration and comparators events. The size of the internal
counter is 16 bits.
 A comparator used to generate events according to the internal counter value. It also computes the PWMx
output waveform according to the configuration.
Comparator
PWMx
output waveform
Internal
Counter
Clock
Selector
inputs
from clock
generator
inputs from
APB bus
Channel