Datasheet

1023
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
41. Pulse Width Modulation Controller (PWM)
41.1 Description
The PWM macrocell controls several channels independently. Each channel controls one square output
waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through
the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock
generator provides several clocks resulting from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering
system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
41.2 Embedded Characteristics
 Four channels, one 16-bit counter per channel
 Common clock generator, providing Thirteen Different Clocks
 A Modulo n counter providing eleven clocks
 Two independent Linear Dividers working on modulo n counter outputs
 Independent channel programming
 Independent Enable Disable Commands
 Independent Clock Selection
 Independent Period and Duty Cycle, with Double Buffering
 Programmable selection of the output waveform polarity
 Programmable center or left aligned output waveform