SAM9G45 Atmel | SMART ARM-based Embedded MPU DATASHEET Description The Atmel® | SMART ARM926EJ-S™-based SAM9G45 embedded microprocessor unit (eMPU) features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO.
Features 2 400 MHz ARM926EJ-S ARM® Thumb® Processor ̶ 32 Kbytes Data Cache, 32 Kbytes Instruction Cache, MMU Memories ̶ DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR ̶ External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash®, SLC NAND Flash with ECC ̶ 64 Kbytes internal SRAM, single-cycle access at system speed or processor speed through TCM interface ̶ 64 Kbytes internal ROM, embedding bootstrap routine Peripherals ̶ LCD Controller (LCDC) supporting STN
Block Diagram System Controller TST PCK0–PCK1 DRXD DTXD AIC PIO FIQ IRQ XIN XOUT ITCM VDDBU NRST POR VDDCORE POR MMU DTCM PIT BM S GS JTA DCache 32 Kbytes Bus Interface I Backup Section 128-bit RC GPBR OSC 32K RTT SHDWC RTC DDR_A0–DDR_A13 DDR_D0–DDR_D15 DDR_VREF DDR_DQM[0..1] DDR_DQS[0..
2. Signal Description Table 2-1 gives details on the signal names classified by peripheral. Table 2-1. Signal Description List Signal Name Function Type Active Level Reference Voltage Comments Power Supplies VDDIOM0 DDR2 I/O Lines Power Supply Power 1.65–1.95 V VDDIOM1 EBI I/O Lines Power Supply Power 1.65–1.95 V or 3.0–3.6 V VDDIOP0 Peripherals I/O Lines Power Supply Power 1.65–3.6 V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65–3.
Table 2-1. Signal Name Signal Description List (Continued) Function Type Active Level Reference Voltage Comments Shutdown, Wakeup Logic SHDN Shutdown Control WKUP Wake-Up Input Output VDDBU Driven at 0V only. 0: The device is in backup mode 1: The device is running (not in backup mode).
Table 2-1.
Table 2-1.
Table 2-1.
Table 2-1.
Table 2-1.
3. Package and Pinout The SAM9G45 is delivered in a 324-ball TFBGA Green-compliant package. 3.1 324-ball TFBGA Package Outline Figure 3-1 shows the orientation of the 324-ball TFBGA package. A detailed mechanical description is given in Section 46. “Mechanical Characteristics”. Figure 3-1. Orientation of the 324-ball TFBGA Package Bottom View V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3.2 324-ball TFBGA Package Pinout Table 3-1.
Table 3-1.
Table 3-1.
4. Power Considerations 4.1 Power Supplies The SAM9G45 has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1. Table 4-1. SAM9G45 Power Supply Pins Pin(s) Item(s) powered Range Typical Ground 0.9–1.1 V 1.0V GNDCORE 1.65–1.95 V 1.8V 1.65–1.95 V 1.8V 3.0–3.6 V 3.3V 1.65–1.95 V 1.8V 3.0–3.6 V 3.3V 1.8–3.
4.2.1 Power-up Sequence Figure 4-1. VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > VOH VOH VDDIO > VIH VIH VDDCORE VDDCOREtyp VT+ t <---- tRST ---> <- t1 -> <------------ t2 -----------> Core Supply POR Output SLCK VDDCORE and VDDBU are controlled by the internal PORs (Power-on Reset) to guarantee that these power sources reach their target values prior to the release of POR.
4.2.2 Power-down Sequence To ensure that the device does not operate outside the operating conditions defined in Section 4.1 “Power Supplies”, it is good practice to first place the device in reset state before removing its power supplies. No specific sequencing is required with respect to its supply channels as long as the NRST line is held active during the power-down phase. Figure 4-2.
5. Memories Figure 5-1.
5.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5.
Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus. Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
5.3 I/O Drive Selection and Delay Control 5.3.1 I/O Drive Selection The aim of this control is to adapt the signal drive to the frequency. Two bits allow the user to select High or Low drive for memories data/address/ctrl signals. 5.3.2 Setting the bit [17], EBI_DRIVE, in the CCFG_EBICSA register of the matrix allows to control the drive of the EBI. Setting the bit [18], DDR_DRIVE, in the CCFG_EBICSA register of the matrix allows to control the drive of the DDR.
D[31,16]on PIOC[31:16] controlled by two registers, DELAY3 and DELAY4, located in the HSMC3 user interface ̶ D[16] <=> DELAY3[3:0], ̶ D[17] <=> DELAY3[7:4],..., ̶ D[22] <=> DELAY3[27:24], ̶ PC[23] <=> DELAY3[31:28] ̶ D[24] <=> DELAY4[3:0], ̶ D[25] <=> DELAY4[7:4],..., ̶ D[30] <=> DELAY4[27:24], ̶ D[31] <=> DELAY4[31:28] A[25:0], controlled by four registers, DELAY5, DELAY6, DELAY7and DELAY8, located in the HSMC3 user interface ̶ A[0] <=> DELAY5[3:0], ̶ A[1] <=> DELAY5[7:4],...
6. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. 6.
6.2 System Controller Block Diagram Figure 6-1. SAM9G45 System Controller Block Diagram System Controller VDDCORE Powered irq0–irq2 fiq periph_irq[2..
6.3 Chip Identification The SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. 6.4 Chip ID: 0x819B05A2 Ext ID: 0x00000004 JTAG ID: 05B2_703F ARM926 TAP ID: 0x0792603F Backup Section The SAM9G45 features a Backup Section that embeds: RC Oscillator Slow Clock Oscillator SCKCR RTT RTC Shutdown Controller 128-bit backup registers A part of RSTC This section is powered by the VDDBU rail.
7. Peripherals 7.1 Peripheral Mapping As shown in Figure 5-1 “SAM9G45 Memory Mapping”, the peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. 7.2 Peripheral Identifiers Table 7-1 defines the Peripheral Identifiers of the SAM9G45.
Table 7-1. SAM9G45 Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic 26 ISI 27 UDPHS 29 MCI1 30 Reserved 31 AIC Peripheral Name External Interrupt Image Sensor Interface USB High Speed Device Port High Speed Multimedia Card Interface 1 – Advanced Interrupt Controller 7.3 Peripheral Interrupts and Clock Control 7.3.
7.4.1 PIO Controller A Multiplexing Table 7-2.
7.4.2 PIO Controller B Multiplexing Table 7-3.
7.4.3 PIO Controller C Multiplexing Table 7-4.
7.4.4 PIO Controller D Multiplexing Table 7-5.
7.4.5 PIO Controller E Multiplexing Table 7-6.
8. ARM926EJ-S Processor Overview 8.1 Description The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density.
8.
8.3 Block Diagram Figure 8-1.
8.4 ARM9EJ-S Processor 8.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: ARM state: 32-bit, word-aligned ARM instructions. THUMB state: 16-bit, halfword-aligned Thumb instructions. Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 8.4.
8.4.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: User mode is the usual ARM program execution state. It is used for executing most application programs Fast Interrupt (FIQ) mode is used for handling fast interrupts.
Table 8-1.
The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: Constraints on the use of registers Stack conventions Argument passing and result return For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set.
8.4.7.2 Exceptions 8.4.7.3 Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are: Fast interrupt (FIQ) Normal interrupt (IRQ) Data and Prefetched aborts (Abort) Undefined instruction (Undefined) Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline.
8.4.8 ARM Instruction Set Overview The ARM instruction set is divided into: Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM Technical Reference Manual. Table 8-2 gives the ARM instruction mnemonic list.
8.4.9 New ARM Instruction Set . Table 8-3.
8.4.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: Branch instructions Data processing instructions Load and Store instructions Load and Store multiple instructions Exception-generating instruction Table 8-4 gives the Thumb instruction mnemonic list. Table 8-4.
8.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: ARM9EJ-S Caches (ICache, DCache and write buffer) TCM MMU Other system options To control these features, CP15 provides 16 additional registers. See Table 8-5. Table 8-5. CP15 Registers Register 1. 2.
8.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
8.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE®, and Linux®. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
8.6.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access.
8.7 Caches and Write Buffer The ARM926EJ-S contains a 32 Kbyte Instruction Cache (ICache), a 32 Kbyte Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache.
The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 8.7.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region.
8.8 Tightly-Coupled Memory Interface 8.8.1 TCM Description The ARM926EJ-S processor features a Tightly-coupled Memory (TCM) interface, which enables separate instruction and data TCMs (ITCM and DTCM) to be directly reached by the processor. TCMs are used to store real-time and performance critical code, they also provide a DMA support mechanism. Unlike AHB accesses to external memories, accesses to TCMs are fast and deterministic and do not incur bus penalties.
8.9 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: 8.9.
9. SAM9G45 Debug and Test 9.1 Description The SAM9G45 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
Block Diagram Figure 9-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test ARM9EJ-S TST ICE-RT ARM926EJ-S DTXD PDC DBGU PIO 9.
9.4 Application Examples 9.4.1 Debug Environment Figure 9-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 9-2.
9.4.2 Test Environment Figure 9-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 9-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Chip n SAM9G45 Chip 2 Chip 1 SAM9G45-based Application Board In Test 9.5 Debug and Test Pin Description Table 9-1.
9.6 Functional Description 9.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 9.6.2 EmbeddedICE The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9G45 Debug Unit Chip ID value is 0x819B 05A2 and the extended ID is 0x00000004 on 32-bit width.
9.6.6 JID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 MANUFACTURER IDENTITY • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 5B27 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 05B2_703F.
10. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities the memory layout can be changed with two parameters. REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once the system has boot. BMS allows the user to layout to 0x0, when convenient, the ROM or an external memory. This is done by hardware at reset.
10.2 Flow Diagram The boot program implements the algorithm shown in Figure 10-1. Figure 10-1.
10.3 Device Initialization 10.3.1 Clock at Start Up At boot start up, the processor clock (PCK) and the master clock (MCK) are found on the slow clock. The slow clock can be an external 32 kHz crystal oscillator or the internal RC oscillator. By default the slow clock is the internal RC oscillator. Its frequency is not precise and is between 20 kHz and 40 kHz. Its start up is much faster than an external 32 kHz quartz.
10.4 NVM Boot 10.4.1 NVM Bootloader Program Description Figure 10-2. NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Yes Valid code detection in NVM NVM contains valid code Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
Figure 10-3. Remap Action after Download Completion 0x0000_0000 0x0000_0000 Internal ROM REMAP Internal SRAM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 0x0040_0000 0x0040_0000 Internal ROM Internal ROM The NVM bootloader program initializes the NVM. It initializes the required PIO. It sets the right peripheral depending on the NVM and tries to access the memory.
10.4.2 Valid Code Detection There are two kinds of valid code detection. Depending on the NVM bootloader, either one or both of them is used. 10.4.2.1 ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM instructions for either branch or load PC with PC relative addressing. Figure 10-4. LDR Opcode 31 1 Figure 10-5.
10.4.3 NVM Bootloader Sequence Figure 10-7. NVM Bootloader Sequence Diagram Device Setup NAND Flash Boot Yes Copy from NAND Flash to SRAM Run NAND Flash Bootloader Yes Copy from SD Card to SRAM Run SD Card Bootloader Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from TWI EEPROM to SRAM Run TWI EEPROM Bootloader No SD Card Boot No SPI Flash Boot No TWI EEPROM Boot No SAM-BA Monitor 10.4.3.1 NAND Flash Boot The NAND Flash bootloader program uses the EBI CS3.
Supported NAND Flash Devices The supported SLC small block NAND Flash devices that are described in Table 10-2. Table 10-2. Supported SLC Small Block NAND Flash Device ID Size (Mbytes) Page Size (bytes) Block Size (bytes) Bus Width Voltage (V) 0x6E 1 256 4096 8 5 0x64 2 256 4096 8 5 0x6B 4 512 8196 8 5 0xE8 1 256 4096 8 3.3 0xEC 1 256 4096 8 3.3 0xEA 2 256 4096 8 3.3 0xE3 4 512 8196 8 3.3 0xE5 4 512 8196 8 3.3 0xD6 8 512 8196 8 3.
It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done using the Continuous Read command from address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. Supported DataFlash Devices The SPI Flash Boot program supports the DataFlash devices listed in Table 10-3. Table 10-3.
Table 10-4.
10.5 SAM-BA Monitor If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched. The SAM-BA Monitor principle is to: ̶ Initialize DBGU and USB ̶ Check if USB Device enumeration has occurred. ̶ Check if characters have been received on the DBGU. ̶ Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 10-5 on page 70. Figure 10-8.
10.5.1 Command List Table 10-5.
10.5.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 baud, 8 bits of data, no parity, 1 stop bit. 10.5.2.1 Supported External Crystal/External Clocks The SAM-BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both external crystal and external clock. 10.5.2.2 Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate.
10.5.3 USB Device Port 10.5.3.1 Supported External Crystal / External Clocks The only frequency supported by SAM-BA Monitor to allow USB communication is a 12 MHz crystal or external clock. 10.5.3.2 USB class The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ® , beginning with Windows 98SE®. The CDC document, available at www.usb.
11. Reset Controller (RSTC) 11.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 11.2 Embedded Characteristics The Reset Controller is based on two Power-on Reset cells, one on VDDBU and one on VDDCORE.
11.4 Functional Description 11.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer. backup_nreset: Affects all the peripherals powered by VDDBU. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin.
11.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
11.4.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time.
11.4.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during three Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise.
11.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup.
11.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
11.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts three Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.
11.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: Backup Reset Wake-up Reset Watchdog Reset Software Reset User Reset Particular cases are listed below: When in User Reset: ̶ ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated.
11.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
11.5 Reset Controller (RSTC) User Interface Table 11-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 Status Register 0x08 Note: Access Reset Backup Reset RSTC_CR Write-only – – RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read/Write – 0x0000_0001 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
11.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFD00 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. • EXTRST: External Reset 0: No effect.
11.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFD04 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
11.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFD08 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset.
12. Real-time Timer (RTT) 12.1 Description The Real-time Timer (RTT) is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 12.2 Embedded Characteristics 12.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR.
12.5 Real-time Timer (RTT) User Interface Table 12-1.
12.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0xFFFFFD20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216.
12.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0xFFFFFD24 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.
12.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0xFFFFFD28 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
12.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0xFFFFFD2C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR.
13. Real-time Clock (RTC) 13.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
13.4 Product Dependencies 13.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 13.4.2 Interrupt The RTC Interrupt is connected to interrupt source 1 (IRQ1) of the advanced interrupt controller. This interrupt line is due to the OR-wiring of the system peripheral interrupt lines (System Timer, Real-time Clock, Power Management Controller, Memory Controller, etc.).
13.5.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed.
Figure 13-2.
13.6 Real-time Clock (RTC) User Interface Table 13-1.
13.6.1 RTC Control Register Name: RTC_CR Address: 0xFFFFFDB0 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0: No effect. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters.
13.6.2 RTC Mode Register Name: RTC_MR Address: 0xFFFFFDB4 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected. All non-significant bits read zero.
13.6.3 RTC Time Register Name: RTC_TIMR Address: 0xFFFFFDB8 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units.
13.6.4 RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFDBC Access: Read/Write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19–20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00–99 (BCD). The lowest four bits encode the units.
13.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFDC0 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0: The second-matching alarm is disabled. 1: The second-matching alarm is enabled.
13.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFDC4 Access: Read/Write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0: The month-matching alarm is disabled. 1: The month-matching alarm is enabled.
13.6.7 RTC Status Register Name: RTC_SR Address: 0xFFFFFDC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0: Time and calendar registers cannot be updated. 1: Time and calendar registers can be updated. • ALARM: Alarm Flag 0: No alarm matching condition occurred.
13.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFDCC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0: No effect.
13.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFDD0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0: No effect.
13.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFDD4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0: No effect.
13.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFDD8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
13.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFDDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
14. Periodic Interval Timer (PIT) 14.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 14.2 14.3 Embedded Characteristics Includes a 20-bit Periodic Counter, with less than 1µs accuracy Includes a 12-bit Interval Overlay Counter Real-time OS or Linux/WinCE compliant tick generator Block Diagram Figure 14-1.
14.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
14.5 Periodic Interval Timer (PIT) User Interface Table 14-1.
14.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFD30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
14.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFD34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
14.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFD38 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
14.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFD3C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
15. Watchdog Timer (WDT) 15.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 15.2 15.
15.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 15-2.
15.5 Watchdog Timer (WDT) User Interface Table 15-1.
15.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0xFFFFFD40 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
15.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0xFFFFFD44 Access: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 11 22 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
15.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0xFFFFFD48 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
16. Shutdown Controller (SHDWC) 16.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 16.2 Embedded Characteristics The Shutdown Controller is supplied on VDDBU and allows a software-controllable shutdown of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power supply. 16.3 Block Diagram Figure 16-1.
16.5 Product Dependencies 16.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 16.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN.
16.7 Shutdown Controller (SHDWC) User Interface Table 16-2.
16.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFD10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0: No effect. 1: If KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
16.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFD14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWKEN 16 RTTWKEN 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 – 2 – 1 CPTWK0 0 WKMODE0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None.
16.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFD18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWK 16 RTTWK 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0: No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
17. General Purpose Backup Registers (GPBR) 17.1 Description The System Controller embeds four general-purpose backup registers. 17.2 Embedded Characteristics 17.3 128-bit general-purpose backup registers General Purpose Backup Registers (GPBR) User Interface Table 17-1. Offset 0x0 ... 0xC Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read/Write – ... ...
17.3.
18. Bus Matrix (MATRIX) 18.1 Description The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
18.2.1 Matrix Masters The Bus Matrix of the SAM9G45 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 18-1.
18.2.3 Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following tables. The four DDR ports are connected differently according to the application device. The user can disable the DDR multi-port in the DDR Multi-port Register (bit DDRMP_DIS) in the Chip Configuration User Interface.
Table 18-3. Masters to Slaves Access DDRMP_DIS = 0 Master Slave 0 0 1 ARM ARM 926 Instr. 926 Data 2 3 4&5 6 7 USB Host OHCI ISI LCD PDC DMA DMA DMA 8 9 10 11 Ethernet USB USB Host MAC Device HS EHCI Reserved Internal SRAM 0 X X X X X X - X X X - Internal ROM X X X - - - - - X - - UHP OHCI X X - - - - - - - - - UHP EHCI X X - - - - - - - - - LCD User Int.
Table 18-5. Internal Memory Mapping Master 18.3 RCBx = 0 Slave Base Address BMS = 1 BMS = 0 RCBx = 1 0x0000 0000 Internal ROM EBI NCS0 Internal SRAM Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.
This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. 18.4.
18.5.1.1 Undefined Length Burst Arbitration In order to optimize AHB burst lengths and arbitration, it may be interesting to set a maximum for undefined length bursts (INCR). The Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected from among the following Undefined Length Burst Type (ULBT) possibilities: 1.
18.5.2 Arbitration Priority Scheme The bus Matrix arbitration scheme is organized in priority pools. Round-Robin priority is used inside the highest and lowest priority pools, whereas fix level priority is used between priority pools and inside the intermediate priority pools. For each slave, each master x is assigned to one of the slave priority pools through the Priority Registers for Slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS).
18.6 Write Protect Registers To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
18.7 Bus Matrix (MATRIX) User Interface Table 18-6.
Table 18-6.
18.7.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...MATRIX_MCFG10 Address: 0xFFFFEA00 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – – – ULBT This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register”.
18.7.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...MATRIX_SCFG7 Address: 0xFFFFEA40 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – 15 14 13 12 11 10 9 8 – – – – – – – SLOT_CYCLE 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register”.
• FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
18.7.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...
18.7.4 Bus Matrix Priority Registers B For Slaves Name: MATRIX_PRBS0...
18.7.5 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0xFFFFEB00 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – RCB10 RCB9 RCB8 7 6 5 4 3 2 1 0 RCB7 RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register”.
18.7.6 Chip Configuration User Interface Table 18-7.
18.7.6.
18.7.6.
18.7.6.3 EBI Chip Select Assignment Register Name: CCFG_EBICSA Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – DDR_DRIVE 15 14 13 12 11 10 9 8 – – – – – – – EBI_DBPUC 16 EBI_DRIVE 7 6 5 4 3 2 1 0 – – EBI_CS5A EBI_CS4A EBI_CS3A – EBI_CS1A – • EBI_CS1A: EBI Chip Select 1 Assignment 0: EBI Chip Select 1 is assigned to the Static Memory Controller.
• DDR_DRIVE: DDR2 dedicated port I/O slew rate selection This allows to avoid overshoots and give the best performances according to the bus load and external memories. 0: Low Drive, optimized for load capacitance < 30 pF. 1: High Drive, optimized for load capacitance < 55 pF. Note: This concerns only stand-alone DDR controller.
18.7.7 Write Protect Mode Register Name: MATRIX_WPMR Address: 0xFFFFEBE4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 18.6 “Write Protect Registers” on page 141. • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
18.7.8 Write Protect Status Register Name: MATRIX_WPSR Address: 0xFFFFEBE8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 18.6 “Write Protect Registers” on page 141. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR.
19. External Memories The product embeds two DDRSDR controllers: DDRSDRC0 and DDRSDRC1. Figure 19-1. DDRSDR Controllers DDRSDRC0 Port 3 Port 2 Port 1 DDR2 or LPDDR Device Port 0 EBI Bus Matrix DDRSDRC1 DDR2 or LPDDR or SDR or LPSDR Device CompactFlash Controller Compact Flash Device NAND Flash Controller NAND Flash Device Static Memory Controller Static Memory Device DDRSDRC0 is a multi-port DDRSDR controller, standalone. It supports only DDR2 and LPDDR devices.
19.1 DDRSDRC0 Multi-port DDRSDR Controller 19.1.1 Description The DDR2 Controller is dedicated to 4-port DDR2/LPDDR support. Data transfers are performed through a 16-bit data bus on one chip select. The DDR2 Controller operates with 1.8V Power Supply (VDDIOM0). 19.1.2 Embedded Characteristics 19.1.2.1 DDR2/LPDDR Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency. Supports AHB Transfers: ̶ Word, Half Word, Byte Access.
19.1.3 DDR2 Controller Block Diagram Figure 19-2. Organization of the DDR2 DDR2 DDR_A0-DDR_A13 DDR_D0-DDR_D15 DDR_CS Bus Matrix DDR_CKE DDR_RAS, DDR_CAS DDR2 LPDDR Controller AHB DDR_CLK,#DDR_CLK DDR_DQS[0..1] DDR_DQM[0..
19.1.4 I/O Lines Description Table 19-1. DDR2 I/O Lines Description Name Function Type Active Level DDR2/LPDDR Controller DDR_D0–DDR_D15 Data Bus I/O DDR_A0–DDR_A13 Address Bus Output DDR_DQM0–DDR_DQM1 Data Mask Output DDR_DQS0–DDR_DQS1 Data Strobe Output DDR_VREF Reference Voltage for DDR2 operations, typically 0.
19.1.6 Implementation Example The following hardware configuration is given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. Figure 19-3. Hardware Configuration - 2 x 8-bit DDR2 DDR_D[0..15] DDR_A[0..
19.2 External Bus Interface (EBI) 19.2.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM.
19.2.2.
19.2.3 EBI Block Diagram Figure 19-4.
19.2.4 I/O Lines Description Table 19-2.
19.2.5 Application Example 19.2.5.1 Hardware Interface Table 19-4 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 19-4.
Table 19-5.
Table 19-5. EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device Signals: EBI_ SDRAM DDRC SDRAMC CAS CAS – – – WE WE – – – Controller CAS SDWE (5) CompactFlash CompactFlash True IDE Mode DDR2/LPDDR NAND Flash SMC NWAIT – – WAIT WAIT – Pxx(2) – – CD1 or CD2 CD1 or CD2 – Pxx(2) – – – – CE(3) Pxx(2) – – – – RDY Notes: 1. Not directly connected to the CompactFlash slot.
19.2.6 Product Dependencies 19.2.6.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 19.2.
external CompactFlash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.
Table 19-7.
Figure 19-7. CompactFlash Read/Write Control Signals External Bus Interface SMC CompactFlash Logic A23 1 1 0 1 0 0 CFOE CFWE 1 1 A22 NRD_NOE NWR0_NWE 0 1 1 Table 19-8.
Application Example Figure 19-8 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus.
19.2.7.7 NAND Flash Support External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices. External Bus Interface The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the EBI_CS3A field in the CCFG_EBICSA register to the appropriate value enables the NAND Flash logic. For details on this register, refer to Section 18. “Bus Matrix (MATRIX)”.
NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines.
19.2.8 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 19.2.8.1 2 x 8-bit DDR2 on EBI Figure 19-11. Hardware Configuration - 2 x 8-bit DDR2 on EBI EBI_SDA10 EBI_SDA10 Software Configuration - 2 x 8-bit DDR2 on EBI Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Assignment Register located in the bus matrix memory space.
19.2.8.2 16-bit LPDDR on EBI Figure 19-12. Hardware Configuration - 16-bit LPDDR on EBI Software Configuration - 16-bit LPDDR on EBI The following configuration has to be performed: Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. Initialize the DDR2 Controller depending on the LPDDR device and system bus frequency. The LPDDR initialization sequence is described in Section 21.4.
19.2.8.3 16-bit SDRAM Figure 19-13. Hardware Configuration - 16-bit SDRAM Software Configuration - 16-bit SDRAM The following configuration has to be performed: Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits.
19.2.8.4 2 x 16-bit SDRAM Figure 19-14. Hardware Configuration - 2 x 16-bit SDRAM A[1..14] D[0..31] SDRAM MN1 VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM0 DQM1 15 39 CAS RAS WE R1 470K 17 18 16 19 MN2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
19.2.8.5 8-bit NAND Flash Figure 19-15. Hardware Configuration - 8-bit NAND Flash D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
19.2.8.6 16-bit NAND Flash Figure 19-16. Hardware Configuration - 16-bit NAND Flash D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
19.2.8.7 NOR Flash on NCS0 Figure 19-17. Hardware Configuration - NOR Flash on NCS0 D[0..15] A[1..
19.2.8.8 CompactFlash Figure 19-18. Hardware Configuration - CompactFlash MEMORY & I/O MODE D[0..
Software Configuration - CompactFlash The following configuration has to be performed: 184 Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 and/or Slot 1 by setting the bit EBI_CS4A and/or EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. The address line A23 is to select I/O (A23 = 1) or Memory mode (A23 = 0) and the address line A22 for REG function.
19.2.8.9 CompactFlash True IDE Figure 19-19. Hardware Configuration - CompactFlash True IDE TRUE IDE MODE D[0..
Software Configuration - CompactFlash True IDE The following configuration has to be performed: Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 and/or Slot 1 by setting the bit EBI_CS4A and/or EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. The address line A21 is to select Alternate True IDE (A21 = 1) or True IDE (A21 = 0) modes.
20. Static Memory Controller (SMC) 20.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
20.4 Application Example 20.4.1 Hardware Interface Figure 20-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NRD NWR0/NWE A2 - A25 A2 - A18 A0 - A16 NRD OE NWR1/NBS1 WE 128K x 8 SRAM D16 - D23 D24-D31 D0 - D7 A0 - A16 NRD Static Memory Controller 20.
20.6 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 20-2).
Figure 20-3. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Figure 20-4.
20.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
20.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 20-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused.
20.8 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 20.8.
20.8.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
20.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 20.8.2.
Figure 20-11.
20.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 20-12. The write cycle starts with the address setting on the memory address bus. 20.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3.
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 20.8.3.
Figure 20-14. WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 20.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 20-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal.
20.8.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
20.9 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 20.9.1 Chip Select Wait States The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one.
in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 20-19. Figure 20-17.
Figure 20-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[31:0] write cycle (WRITE_MODE = 1) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) 20.9.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
20.9.3.2 Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 214). 20.9.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document.
Figure 20-20. TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS tpacc D[31:0] TDF = 2 clock cycles NRD controlled read operation Figure 20-21.
20.10.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 20-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
Figure 20-23. TDF Optimization Disabled (TDF_MODE = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[31:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 20-24.
Figure 20-25. TDF_MODE = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 20.11 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
20.11.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 20-26.
Figure 20-27.
20.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 20-28 and Figure 20-29. After deassertion, the access is completed: the hold step of the access is performed.
Figure 20-29.
20.11.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
20.12 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
Figure 20-32. Clock Rate Transition Occurs While the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 1 1 1 1 1 3 2 2 NCS NWE_CYCLE = 3 NWE_CYCLE = 7 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State Figure 20-33.
20.13 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
The programming of the read timings in page mode is described in Table 20-7. Table 20-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
Figure 20-35.
20.14 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8. The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT).
20.15 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 20-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 20-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 20-8.
20.15.1 SMC Setup Register Name: SMC_SETUP[0..
20.15.2 SMC Pulse Register Name: SMC_PULSE[0..
20.15.3 SMC Cycle Register Name: SMC_CYCLE[0..5] Address: 0xFFFFE808 [0], 0xFFFFE818 [1], 0xFFFFE828 [2], 0xFFFFE838 [3], 0xFFFFE848 [4], 0xFFFFE858 [5] Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
20.15.4 SMC MODE Register Name: SMC_MODE[0..5] Address: 0xFFFFE80C [0], 0xFFFFE81C [1], 0xFFFFE82C [2], 0xFFFFE83C [3], 0xFFFFE84C [4], 0xFFFFE85C [5] Access: Read/Write 31 30 – – 23 22 21 20 – – – TDF_MODE 15 14 13 12 – – 7 6 – – 29 28 PS DBW 5 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 TDF_CYCLES 11 10 9 8 – – – BAT 1 0 3 2 – – WRITE_MODE READ_MODE • READ_MODE: 1: The read operation is controlled by the NRD signal.
• BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
20.15.5 SMC DELAY I/O Register Name: SMC_DELAY 1-8 Address: 0xFFFFE8C0 [1], 0xFFFFE8C4 [2], 0xFFFFE8C8 [3], 0xFFFFE8CC [4], 0xFFFFE8D0 [5], 0xFFFFE8D4 [6], 0xFFFFE8D8 [7], 0xFFFFE8DC [8] Access: Read/Write 31 30 29 28 27 26 Delay8 23 22 21 20 19 18 Delay6 15 14 13 6 17 16 12 11 10 9 8 1 0 Delay3 5 Delay2 • Delay x Gives the number of elements in the delay line.
21. DDR SDR SDRAM Controller (DDRSDRC) 21.1 Description The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDR-SDRAM device and external 16-bit DDR-SDRAM device.
21.
21.3 DDRSDRC Module Diagram Figure 21-1.
21.4 Initialization Sequence The addresses given are for example purposes only. The real address depends on implementation in the product. 21.4.1 SDR-SDRAM Initialization The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 21.8.8 on page 267). 2. Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.
21.4.2 Low-power DDR1-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 21.8.8 on page 267). 2. Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous timing (trc, tras, etc.), number of columns, rows, cas latency. See Section 21.8.3 on page 258, Section 21.8.
21.4.3 DDR2-SDRAM Initialization The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 21.8.8 on page 267). 2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, CAS latency and output drive strength) (see Section 21.8.3 on page 258, Section 21.
Section 21.8.1 on page 256). Perform a write access to any DDR2-SDRAM address to acknowledge this command 12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register, the application must configure the MODE field value to 4 in the Mode Register (see Section 21.8.1 on page 256). Performs a write access to any DDR2-SDRAM location twice to acknowledge these commands. 13. Program DLL field into the Configuration Register (see Section 21.8.
21.5 Functional Description 21.5.1 SDRAM Controller Write Cycle The DDRSDRC allows burst access or single access in normal mode (DDRSDRC_MR.MODE = 000). Whatever the access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance. The SDRAM device is programmed with a burst length equal to 8. This determines the length of a sequential data input by the write command that is set to 8.
Figure 21-2. Single Write Access, Row Closed, Low-power DDR1-SDRAM Device SDCLK Row a A[12:0] COMMAND PRCHG NOP NOP col a ACT NOP WRITE NOP 00 BA[1:0] DQS[1:0] DM[1:0] 3 D[15:0] Da Trp = 2 Figure 21-3.
Figure 21-4. Single Write Access, Row Closed, SDR-SDRAM Device SDCLK A[12:0] Row a COMMAND NOP PRCHG NOP ACT Col a NOP BST NOP 00 BA[1:0] 3 DM[1:0] 0 D[31:0] 3 DaDb Trp = 2 Figure 21-5.
Figure 21-6. Burst Write Access, Row Closed, DDR2-SDRAM Device SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da Dc Dd De Df Dg Dh Trcd = 2 Trp = 2 Figure 21-7.
Figure 21-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device SDCLK A[12:0] col a COMMAND NOP BA[1:0] col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Dc Dd De Df Dg Dh Da Db Twrd = BL/2 +2 = 8/2 +2 = 6 Twr = 1 In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data. See Figure 21-9.
Figure 21-10. SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da 3 Da Db Db Data masked twtr 21.5.2 SDRAM Controller Read Cycle The DDRSDRC allows burst access or single access in normal mode (DDRSDRC_MR.MODE =000). Whatever access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
For a definition of timing parameters, refer to Section 21.8.3 “DDRSDRC Configuration Register” on page 258. Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached.
Figure 21-12. Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Device SDCLK A[12:0] COMMAND NOP PRCHG NOP Row a Column a ACT NOP READ BA[1:0] 0 DQS[1] DQS[0] DM[1:0] 3 Da D[15:0] TRP TRCD Db Latency = 3 Figure 21-13.
Figure 21-14. Burst Read Access, Latency = 2, Low-power DDR1-SDRAM Devices SDCLK Col a A[12:0] COMMAND BA[1:0] NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Dc Dd De Db Dc Df Dg Dh Latency = 2 Figure 21-15.
Figure 21-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a NOP READ NOP BST NOP 0 DQS[1:0] DM[3:0] F D[31:0] DaDb DcDd DeDf Dg Dh Latency = 2 21.5.3 Refresh (Auto-refresh Command) An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these autorefresh commands periodically.
parameters and Drive Strength (DS). These parameters are set during the initialization phase.
Figure 21-18. Self Refresh Mode Entry, Timeout = 1 or 2 SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Trp 64 or 128 wait states Enter Self refresh Mode Figure 21-19.
Figure 21-20. Self Refresh and Automatic Update SDCLK Pasr-Tcr-Ds A[12:0] COMMAND NOP PRCHG NOP MRS NOP NOP ARFSH CKE BA[1:0] 0 2 Enter Self Refresh Mode Tmrd Trp Update Extended Mode register Figure 21-21.
21.5.4.2 Power-down Mode This mode is activated by setting the low-power command bits [LPCB] to ‘10’. Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is greater than in self refresh mode. This state is similar to normal mode (No low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers are deactivated as soon the SDRAM device is no longer accessible.
21.5.4.3 Deep Power-down Mode The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is enabled, the DDRSDRC leaves normal mode (DDRSDRC_MR.MODE = 000) and the controller is frozen.
21.5.5 Multi-port Functionality The SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a row in a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must be performed to open a bank: Precharge and Active command with respect to Trp timing.
2. Single cycles: When a slave is currently doing a single access. 3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined length, predicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is generated at the end of each four beat boundary inside the INCR transfer. 4.
21.5.6 Write Protected Registers To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
21.6 Software Interface/SDRAM Organization, Address Mapping The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See Section 21.8.3 “DDRSDRC Configuration Register” on page 258. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.
Table 21-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 Row[13:0] Bk[1:0] 6 5 4 3 2 1 Column[8:0] Row[13:0] Bk[1:0] Note: 17 M0 Column[9:0] Row[13:0] 0 M0 Column[10:0] M0 1. SDR-SDRAM devices with eight columns in 16-bit mode are not supported. 21.6.2 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width Table 21-5.
21.7 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, DDRSDRC_DELAY1-8.
21.8 DDR SDR SDRAM Controller (DDRSDRC) User Interface The User Interface is connected to the APB bus. The DDRSDRC is programmed using the registers listed in Table 21-8. Table 21-8.
21.8.1 DDRSDRC Mode Register Name: DDRSDRC_MR Address: 0xFFFFE600 (0), 0xFFFFE400 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – – – MODE This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
21.8.2 DDRSDRC Refresh Timer Register Name: DDRSDRC_RTR Address: 0xFFFFE604 (0), 0xFFFFE404 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 1 0 COUNT 3 2 COUNT This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
21.8.3 DDRSDRC Configuration Register Name: DDRSDRC_CR Address: 0xFFFFE608 (0), 0xFFFFE408 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – ACTBST – EBISHARE 15 14 13 12 11 10 9 8 – – DIS_DLL DIC/DS 2 1 – OCD 7 6 5 DLL 4 CAS 3 NR 0 NC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
• CAS: CAS Latency Reset value is 2 cycles. CAS DDR2 CAS Latency SDR CAS Latency 000 Reserved Reserved 001 Reserved Reserved 010 Reserved 2 011 3 3 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved • DLL: Reset DLL Reset value is 0. This field defines the value of Reset DLL. 0: Disable DLL reset. 1: Enable DLL reset. This value is used during the power-up sequence. Note: This field is found only in DDR2-SDRAM devices.
• EBISHARE: External Bus Interface is Shared The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..) Reset value is 0. 0: Only the DDR controller function is used. 1: The DDR controller shares the EBI with another memory controller (SMC, NAND,..) • ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y Reset value is 0. 0: After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access.
21.8.4 DDRSDRC Timing Parameter 0 Register Name: DDRSDRC_TPR0 Address: 0xFFFFE60C (0), 0xFFFFE40C (1) Access: Read/Write 31 30 29 28 TMRD 23 22 27 26 REDUCE_WRRD 21 20 19 14 18 13 6 17 16 9 8 1 0 TRP 12 11 10 TRC 7 24 TWTR TRRD 15 25 TWR 5 TRCD 4 3 2 TRAS This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271. • TRAS: Active to Precharge Delay Reset value is 5 cycles.
• TWTR: Internal Write to Read Delay Reset value is 0. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.
21.8.5 DDRSDRC Timing Parameter 1 Register Name: DDRSDRC_TPR1 Address: 0xFFFFE610 (0), 0xFFFFE410 (1) Access: Read/Write 31 30 29 28 – – – – 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 2 1 0 TXSRD 15 14 13 12 TXSNR 7 6 5 – – – 4 3 TRFC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271. • TRFC: Row Cycle Delay Reset value is 8 cycles.
21.8.6 DDRSDRC Timing Parameter 2 Register Name: DDRSDRC_TPR2 Address: 0xFFFFE614 (0), 0xFFFFE414 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 1 0 – 7 TRTP 6 5 TRPA 4 3 2 TXARDS TXARD This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271. • TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
21.8.7 DDRSDRC Low-power Register Name: DDRSDRC_LPR Address: 0xFFFFE61C (0), 0xFFFFE41C (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – APDE 15 14 11 10 9 8 – – 7 6 – UPD_MR 13 12 TIMEOUT 5 DS 4 3 PASR TCR 2 1 CLK_FR 0 LPCB • LPCB: Low-power Command Bit Reset value is “00”. 00: Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
• TCR: Temperature Compensated Self Refresh Reset value is “0”. This field is unique to Low-power SDRAM. It is used to program the refresh interval during self refresh mode, depending on the case temperature of the low-power SDRAM. The values of this field are dependent on Low-power SDRAM devices. After the initialization sequence, as soon as TCR field is modified, Extended Mode Register is accessed automatically and TCR bits are updated.
21.8.8 DDRSDRC Memory Device Register Name: DDRSDRC_MD Address: 0xFFFFE620 (0), 0xFFFFE420 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – DBW – MD This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271. • MD: Memory Device Indicates the type of memory used.
21.8.9 DDRSDRC DLL Register Name: DDRSDRC_DLL Address: 0xFFFFE624 (0), 0xFFFFE424 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 MDVAL 7 6 5 4 3 2 1 0 – – – – – MDOVF MDDEC MDINC The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.
21.8.10 DDRSDRC High Speed Register Name: DDRSDRC_HS Address: 0xFFFFE62C (0), 0xFFFFE42C (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DIS_ANTICIP_ READ – – – – – – This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
21.8.11 DDRSDRC DELAY I/O Register Name: DDRSDRC_DELAYx [x=1..4] Address: 0xFFFFE640 (0), 0xFFFFE440 (1) Access: Read/Write 31 30 29 28 27 26 DELAY8 23 22 21 14 20 19 18 13 6 16 12 11 10 9 8 1 0 DELAY3 5 DELAY2 • DELAYx: Delay1..Delay8 Gives the number of elements in the delay line.
21.8.12 DDRSDRC Write Protect Mode Register Name: DDRSDRC_WPMR Address: 0xFFFFE6E4 (0), 0xFFFFE4E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
21.8.13 DDRSDRC Write Protect Status Register Name: DDRSDRC_WPSR Address: 0xFFFFE6E8 (0), 0xFFFFE4E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR.
22. Error Correction Code Controller (ECC) 22.1 Description NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data.
22.3 Functional Description A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. Over time, some memory locations may fail to program or erase properly.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) hsiao code is used. 24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of 512/2048/4096 8-bit words. 32bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in Figure 22-2 and Figure 22-3. Figure 22-2.
Parity Generation for 512/1024/2048/4096 16-bit Words 276 SAM9G45 [DATASHEET] Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15 (Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word 4th word 1st word 2nd word 3rd word (+) Figure 22-3.
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
22.4 Error Correction Code Controller (ECC) User Interface Table 22-1.
22.4.1 ECC Control Register Name: ECC_CR Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 SRST 24 – 16 – 8 – 0 RST • RST: RESET Parity Provides reset to current ECC by software. 1: Reset ECC Parity registers 0: No effect • SRST: Soft Reset Provides soft reset to ECC block 1: Resets all registers. 0: No effect.
22.4.2 ECC Mode Register Name: ECC_MR Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 28 – – 21 20 – – 13 12 – – 5 4 TYPECORRECT 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PAGESIZE • PAGESIZE: Page Size This field defines the page size of the NAND Flash device. PAGESIZE Description 00 528 words 01 1056 words 10 2112 words 11 4224 words A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia memory organization.
22.4.3 ECC Status Register 1 Name: ECC_SR1 Access: Read-only 31 – 23 – 15 – 7 – 30 MULERR7 22 MULERR5 14 MULERR3 6 MULERR1 29 ECCERR7 21 ECCERR5 13 ECCERR3 5 ECCERR1 28 RECERR7 20 RECERR5 12 RECERR3 4 RECERR1 27 – 19 – 11 – 3 – 26 MULERR6 18 MULERR4 10 MULERR2 2 MULERR0 25 ECCERR6 17 ECCERR4 9 ECCERR2 1 ECCERR0 24 RECERR6 16 RECERR4 8 RECERR2 0 RECERR0 • RECERR0: Recoverable Error 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected.
• RECERR2: Recoverable Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. • ECCERR2: ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes.
• ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 4 register, the error occurred at the location which contains a 1 in the least significant 24 bits. • MULERR4: Multiple Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected.
• MULERR6: Multiple Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected. • RECERR7: Recoverable Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
22.4.4 ECC Status Register 2 Name: ECC_SR2 Access: Read-only 31 – 23 – 15 – 7 – 30 MULERR15 22 MULERR13 14 MULERR11 6 MULERR9 29 ECCERR15 21 ECCERR13 13 ECCERR11 5 ECCERR9 28 RECERR15 20 RECERR13 12 RECERR11 4 RECERR9 27 – 19 – 11 – 3 – 26 MULERR14 18 MULERR12 10 MULERR10 2 MULERR8 25 ECCERR14 17 ECCERR12 9 ECCERR10 1 ECCERR8 24 RECERR14 16 RECERR12 8 RECERR10 0 RECERR8 • RECERR8: Recoverable Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0.
• MULERR9: Multiple Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected. • RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
• ECCERR12: ECC Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0 0: No Errors Detected 1: A single bit error occurred in the ECC bytes. Read ECC Parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits. • MULERR12: Multiple Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected • ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes.
22.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes 22.5.1 ECC Parity Register 0 Name: ECC_PR0 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 3 2 25 – 17 – 9 24 – 16 – 8 1 0 WORDADDR 7 6 5 WORDADDR 4 BITADDR Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.5.
22.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word 22.6.1 ECC Parity Register 0 Name: ECC_PR0 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY0 12 27 – 19 26 – 18 11 10 NPARITY0 7 6 5 WORDADDR0 25 – 17 24 – 16 9 8 1 BITADDR0 0 WORDADD0 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.2 ECC Parity Register 1 Name: ECC_PR1 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY1 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 4 3 2 1 BITADDR1 0 NPARITY1 5 WORDADDR1 WORDADD1 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.3 ECC Parity Register 2 Name: ECC_PR2 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY2 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR2 2 1 BITADDR2 NPARITY2 5 WORDADDR2 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.4 ECC Parity Register 3 Name: ECC_PR3 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY3 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR3 2 1 BITADDR3 NPARITY3 5 WORDADDR3 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.5 ECC Parity Register 4 Name: ECC_PR4 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY4 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR4 2 1 BITADDR4 NPARITY4 5 WORDADDR4 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.6 ECC Parity Register 5 Name: ECC_PR5 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY5 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR5 2 1 BITADDR5 NPARITY5 5 WORDADDR5 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.7 ECC Parity Register 6 Name: ECC_PR6 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY6 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR6 2 1 BITADDR6 NPARITY6 5 WORDADDR6 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.6.8 ECC Parity Register 7 Name: ECC_PR7 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY7 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR7 2 1 BITADDR7 NPARITY7 5 WORDADDR7 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word 22.7.1 ECC Parity Register 0 Name: ECC_PR0 Access: Read-only 31 – 23 0 15 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY0 7 6 5 WORDADDR0 4 27 – 19 NPARITY0 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR0 1 BITADDR0 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.2 ECC Parity Register 1 Name: ECC_PR1 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY1 5 WORDADDR1 4 27 – 19 NPARITY1 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR1 1 BITADDR1 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.3 ECC Parity Register 2 Name: ECC_PR2 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY2 5 WORDADDR2 4 27 – 19 NPARITY2 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADD2 1 BITADDR2 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.4 ECC Parity Register 3 Name: ECC_PR3 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY3 5 WORDADDR3 4 27 – 19 NPARITY3 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR3 1 BITADDR3 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.5 ECC Parity Register 4 Name: ECC_PR4 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY4 5 WORDADDR4 4 27 – 19 NPARITY4 11 0 3 26 – 18 10 2 25 – 17 9 WORDADDR4 1 BITADDR4 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.6 ECC Parity Register 5 Name: ECC_PR5 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY5 5 WORDADDR5 4 27 – 19 NPARITY5 11 0 3 26 – 18 10 2 25 – 17 9 WORDADDR5 1 BITADDR5 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.7 ECC Parity Register 6 Name: ECC_PR6 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY6 5 WORDADDR6 4 27 – 19 NPARITY6 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR6 1 BITADDR6 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.8 ECC Parity Register 7 Name: ECC_PR7 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY7 5 WORDADDR7 4 27 – 19 NPARITY7 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR7 1 BITADDR7 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.9 ECC Parity Register 8 Name: ECC_PR8 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY8 5 WORDADDR8 4 27 – 19 NPARITY8 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR8 1 BITADDR8 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.10 ECC Parity Register 9 Name: ECC_PR9 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY9 5 WORDADDR9 4 27 – 19 NPARITY9 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR9 1 BITADDR9 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.11 ECC Parity Register 10 Name: ECC_PR10 Access: Read-only 31 – 23 0 15 7 30 – 22 29 – 21 14 13 NPARITY10 6 5 WORDADDR10 28 – 20 12 4 27 – 19 NPARITY10 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR10 1 BITADDR10 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.12 ECC Parity Register 11 Name: ECC_PR11 Access: Read-only 31 – 23 0 15 7 30 – 22 29 – 21 14 13 NPARITY11 6 5 WORDADDR11 28 – 20 12 4 27 – 19 NPARITY11 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR11 1 BITADDR11 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.13 ECC Parity Register 12 Name: ECC_PR12 Access: Read-only 31 – 23 0 15 7 30 – 22 29 – 21 14 13 NPARITY12 6 5 WORDADDR12 28 – 20 12 4 27 – 19 NPARITY12 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR12 1 BITADDR12 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.14 ECC Parity Register 13 Name: ECC_PR13 Access: Read-only 31 – 23 0 15 7 30 – 22 29 – 21 14 13 NPARITY13 6 5 WORDADDR13 28 – 20 12 4 27 – 19 NPARITY13 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR13 1 BITADDR13 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.15 ECC Parity Register 14 Name: ECC_PR14 Access: Read-only 31 – 23 0 15 7 30 – 22 29 – 21 14 13 NPARITY14 6 5 WORDADDR14 28 – 20 12 4 27 – 19 NPARITY14 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR14 1 BITADDR14 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
22.7.16 ECC Parity Register 15 Name: ECC_PR15 Access: Read-only 31 – 23 0 15 7 30 – 22 29 – 21 14 13 NPARITY15 6 5 WORDADDR15 28 – 20 12 4 27 – 19 NPARITY15 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR15 1 BITADDR15 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
23. Peripheral DMA Controller (PDC) 23.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 23-1.
23.3 Block Diagram Figure 23-1.
23.4 Functional Description 23.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
These status flags are described in the Peripheral Status Register. 23.4.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix.
23.5 Peripheral DMA Controller (PDC) User Interface Table 23-2.
23.5.1 Receive Pointer Register Name: PERIPH_RPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
23.5.2 Receive Counter Register Name: PERIPH_RCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
23.5.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
23.5.4 Transmit Counter Register Name: PERIPH_TCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
23.5.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
23.5.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
23.5.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
23.5.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
23.5.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
23.5.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0: PDC Receiver channel requests are disabled. 1: PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0: PDC Transmitter channel requests are disabled.
24. Clock Generator 24.1 Description The Clock Generator User Interface is embedded within the Power Management Controller Interface and is described in Section 25.12. However, the Clock Generator registers are named CKGR_. 24.
24.3 Slow Clock Crystal Oscillator The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in Figure 24-2. Figure 24-2. Typical Slow Clock Crystal Oscillator Connection XIN32 XOUT32 GNDOSC 32,768 Hz Crystal 24.4 Slow Clock RC Oscillator The user has to take into account the possible drifts of the RC Oscillator. More details are given in Section 45.2 “DC Characteristics”. 24.
24.5.1 Switch from Internal RC Oscillator to the 32768 Hz Crystal To switch from internal RC oscillator to the 32768 Hz crystal, the programmer must execute the following sequence: 24.5.2 Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator) through the Power management Controller. Enable the 32768 Hz oscillator by setting the bit OSCEN to 1.
24.5.
24.6 Main Oscillator The Main Oscillator is designed for a 12 MHz fundamental crystal. The 12 MHz is an input of the PLLA and the UPLL used to generate the 480 MHz USB High Speed Clock (UPLLCK). Figure 24-4 shows the Main Oscillator block diagram. Figure 24-4. Main Oscillator Block Diagram XIN 12M Main Oscillator Main Clock MAINCK XOUT UPLL UPLLCK PLLA and Divider 24.6.1 PLLA Clock PLLACK Main Oscillator Connections The typical crystal connection is illustrated in Figure 24-5.
from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor. 24.6.4 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin.
24.8 UTMI Bias and Phase Lock Loop Programming The multiplier is built-in to 40 to obtain the USB High Speed 480 MHz. UPLLEN MAINCK UPLL UPLLCK PLLCOUNT SLCK UPLL Counter LOCKU Whenever the UPLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UPLL counter. The UPLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0.
25. Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. 25.2 Embedded Characteristics The Power Management Controller provides all the clock signals to the system.
25.3 Block Diagram Figure 25-1. Power Management Controller Block Diagram PLLACK USBS UHP48M USBDIV+1 USB OHCI UHP12M /4 USB EHCI PCK Processor Clock Controller UPLLCK int Divider MAINCK SLCK Prescaler /1,/2,/4,.../64 X /1 /1.5 /2 SysClk DDR /1 /2 MCK /3 /4 Peripherals Clock Controller ON/OFF Master Clock Controller SLCK MAINCK periph_clk[..] ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] UPLLCK Programmable Clock Controller 25.3.
25.3.1.3 No UDP HS, UHP FS and DDR2 Mode 25.4 Only PLLA is running at 384 MHz, UPLL power consumption is saved USB Device High Speed and Host EHCI High Speed operations are NOT allowed Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8) System Input clock is PLLACK, PCK is 384 MHz MDIV is ‘11’, MCK is 128 MHz DDR2 can be used at up to 128 MHz Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK).
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to the Atmel application note Optimizing Power Consumption of AT91SAM9261-based Systems, literature number 6217. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 25.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 25.9 Programmable Clock Output Controller The PMC controls two signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers.
Code Example: write_register(CKGR_PLLAR,0x00040805) If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles. 3. Setting Bias and High Speed PLL (UPLL) for UTMI The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR. The UTMI Bias must is enabled by setting the BIASEN field in the CKGR_UCKR in the same time.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks. Note: IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and MCKRDY is set.
Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Each enabled peripheral clock corresponds to Master Clock. Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. 25.11 Clock Switching Details 25.11.
25.11.2 Clock Switching Waveforms Figure 25-3. Switch Master Clock from Slow Clock to PLLA Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 25-4.
Figure 25-5. Change PLLA Programming Main Clock PLL Clock LOCK MCKRDY Master Clock Main Clock Write CKGR_PLLR Figure 25-6.
25.12 Power Management Controller (PMC) User Interface Table 25-2.
25.12.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 PCK7 PCK6 PCK5 PCK4 PCK5 PCK4 PCK1 PCK0 7 6 5 4 3 2 1 0 PCK7 UHP – – – DDRCK – – • DDRCK: DDR Clock Enable 0: No effect. 1: Enables the DDR clock. • UHP: USB Host OHCI Clocks Enable 0: No effect. 1: Enables the UHP48M and UHP12M OHCI clocks.
25.12.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 PCK7 PCK6 PCK5 PCK4 PCK5 PCK4 PCK1 PCK0 7 6 5 4 3 2 1 0 PCK7 UHP – – – DDRCK – PCK • PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode.
25.12.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 PCK7 PCK6 PCK5 PCK4 PCK5 PCK4 PCK1 PCK0 7 6 5 4 3 2 1 0 PCK7 UHP – – – DDRCK – PCK • PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled. • DDRCK: DDR Clock Status 0: The DDR clock is disabled.
25.12.4 PMC Peripheral Clock Enable Register Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0: No effect.
25.12.5 PMC Peripheral Clock Disable Register Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0: No effect.
25.12.
25.12.7 PMC UTMI Clock Configuration Register Name: CKGR_UCKR Address: 0xFFFFFC1C Access: Read/Write 31 30 29 28 27 – 26 – 25 – 24 BIASEN 21 20 19 – 18 – 17 – 16 UPLLEN BIASCOUNT 23 22 PLLCOUNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UPLLEN: UTMI PLL Enable 0: The UTMI PLL is disabled. 1: The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
25.12.8 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The Main Oscillator is disabled. 1: The Main Oscillator is enabled. OSCBYPASS must be set to 0.
25.12.9 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled.
25.12.10 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read/Write 31 – 30 – 29 1 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
25.12.
25.12.12 PMC Master Clock Register Name: PMC_MCKR Address: 0xFFFFFC30 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – PLLADIV2 – – 4 3 2 7 6 5 – – – • CSS: Master/Processor Clock Source Selection CSS Clock Source Selection 0 0 Slow Clock is selected. 0 1 Main Clock is selected. 1 0 PLLA Output clock is selected. 1 1 UPLL Output clock is selected.
• MDIV: Master Clock Division MDIV 0 0 Master Clock Division Master Clock is Prescaler Output Clock divided by 1. Warning: SysClk DDR and DDRCK are not available. Master Clock is Prescaler Output Clock divided by 2. 0 1 SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 4. 1 0 SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 3. 1 1 SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
25.12.13 PMC Programmable Clock Register Name: PMC_PCKx Address: 0xFFFFFC40 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SLCKMCK 4 3 2 1 7 6 5 – – – PRES • CSS: Master Clock Selection CSS Clock Source Selection 0 0 Slow Clock or Master Clock may be selected depending on SLCKMCK field. 0 1 Main Clock is selected. 1 0 PLLACK/PLLADIV2 is selected.
25.12.
25.12.
25.12.16 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK5 PCK4 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – LOCKU – – MCKRDY – LOCKA MOSCS • MOSCS: MOSCS Flag Status 0: Main oscillator is not stabilized. 1: Main oscillator is stabilized. • LOCKA: PLLA Lock Status 0: PLLA is not locked 1: PLLA is locked.
25.12.
25.12.
26. Advanced Interrupt Controller (AIC) 26.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and realtime overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
26.3 Block Diagram Figure 26-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 26.4 Application Block Diagram Figure 26-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 26.
26.6 I/O Line Description Table 26-1. 26.7 I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0–IRQn Interrupt 0–Interrupt n Input Product Dependencies 26.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function.
26.8 Functional Description 26.8.1 Interrupt Source Control 26.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
26.8.1.5 Internal Interrupt Source Input Stage Figure 26-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 26.8.1.6 External Interrupt Source Input Stage Figure 26-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg.
26.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: The time the software masks the interrupts. Occurrence, either at the processor level or at the AIC level. The execution time of the instruction in progress when the interrupt occurs. The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
26.8.2.3 Internal Interrupt Edge Triggered Source Figure 26-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 26.8.2.4 Internal Interrupt Level Sensitive Source Figure 26-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 26.8.3 Normal Interrupt 26.8.3.
26.8.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted.
3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: ̶ Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. ̶ De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ.
26.8.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register).
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages.
In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode.
26.9 Advanced Interrupt Controller (AIC) User Interface 26.9.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Table 26-3. Register Mapping Offset Register Name Access Reset 0x00 Source Mode Register 0 0x04 Source Mode Register 1 AIC_SMR0 Read/Write 0x0 AIC_SMR1 Read/Write 0x0 ... ... ... ... ...
26.9.2 AIC Source Mode Register Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 4 3 2 1 0 – – – 5 SRCTYPE PRIOR • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest).
26.9.3 AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
26.9.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
26.9.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
26.9.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 0 7 6 5 – – – IRQID • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
26.9.7 AIC Interrupt Pending Register Name: AIC_IPR Address: 0xFFFFF10C Access: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Pending 0: Corresponding interrupt is not pending.
26.9.8 AIC Interrupt Mask Register Name: AIC_IMR Address: 0xFFFFF110 Access: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Mask 0: Corresponding interrupt is disabled.
26.9.9 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ • NFIQ: NFIQ Status 0: nFIQ line is deactivated. 1: nFIQ line is active. • NIRQ: NIRQ Status 0: nIRQ line is deactivated. 1: nIRQ line is active.
26.9.10 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Enable 0: No effect.
26.9.11 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Disable 0: No effect.
26.9.12 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Clear 0: No effect.
26.9.13 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Set 0: No effect.
26.9.14 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
26.9.15 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
26.9.16 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT • PROT: Protection Mode 0: The Protection Mode is disabled. 1: The Protection Mode is enabled. • GMSK: General Mask 0: The nIRQ and nFIQ lines are normally controlled by the AIC.
26.9.17 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2–PID31: Fast Forcing Enable 0: No effect.
26.9.18 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2–PID31: Fast Forcing Disable 0: No effect.
26.9.
27. Debug Unit (DBGU) 27.1 Description The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
27.3 Block Diagram Figure 27-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control Power-on Reset force_ntrst Table 27-1.
27.4 Product Dependencies 27.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. Table 27-2. I/O Lines Instance Signal I/O Line Peripheral DBGU DRXD PB12 A DBGU DTXD PB13 A 27.4.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
Figure 27-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 27.5.2 Receiver 27.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
Figure 27-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 27.5.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 27-6.
27.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 27-9.
27.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR.
Figure 27-12. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter TXD VDD Disabled Disabled RXD TXD 27.5.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
27.5.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
27.6 Debug Unit (DBGU) User Interface Table 27-3.
27.6.1 Debug Unit Control Register Name: DBGU_CR Address: 0xFFFFEE00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
27.6.
27.6.
27.6.
27.6.
27.6.6 Debug Unit Status Register Name: DBGU_SR Address: 0xFFFFEE14 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0: No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
• TXBUFE: Transmission Buffer Empty 0: The buffer empty signal from the transmitter PDC channel is inactive. 1: The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0: The buffer full signal from the receiver PDC channel is inactive. 1: The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0: COMMTX from the ARM processor is inactive. 1: COMMTX from the ARM processor is active.
27.6.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Address: 0xFFFFEE18 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
27.6.8 Debug Unit Transmit Holding Register Name: DBGU_THR Address: 0xFFFFEE1C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
27.6.
27.6.10 Debug Unit Chip ID Register Name: DBGU_CIDR Address: 0xFFFFEE40 Access: Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 3 EPROC 2 VERSION • VERSION: Version of the Device Values depend upon the version of the device.
• NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8 Kbytes 0 0 1 0 16 Kbytes 0 0 1 1 32 Kbytes 0 1 0 0 Reserved 0 1 0 1 64 Kbytes 0 1 1 0 Reserved 0 1 1 1 128 Kbytes 1 0 0 0 Reserved 1 0 0 1 256 Kbytes 1 0 1 0 512 Kbytes 1 0 1 1 Reserved 1 1 0 0 1024 Kbytes 1 1 0 1 Reserved 1 1 1 0 2048 Kbytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ 420 Size 0 0 0 0 Reserved 0 0 0 1 1
• ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 011
27.6.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Address: 0xFFFFEE44 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
27.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address: 0xFFFFEE48 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0: NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1: NTRST of the ARM processor’s TAP controller is held low.
28. Serial Peripheral Interface (SPI) 28.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
28.3 Block Diagram Figure 28-1. Block Diagram PDC APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt Figure 28-2. Block Diagram AHB Matrix DMA Ch.
28.4 Application Block Diagram Figure 28-3. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 28.5 Signal Description Table 28-1.
28.6 Product Dependencies 28.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 28-2.
28.7 Functional Description 28.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
Figure 28-4. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 28-5.
28.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
28.7.3.1 Master Mode Block Diagram Figure 28-6. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
28.7.3.2 Master Mode Flow Diagram Figure 28-7. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
Figure 28-8 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 28-8.
Figure 28-9 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE are not shown because these flags are managed by the PDC when using the PDC.
28.7.3.4 Transfer Delays Figure 28-10 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15.
28.7.3.10 Peripheral Deselection Without PDC nor DMAC During a transfer of more than one data on a Chip Select without the PDC nor DMAC, the SPI_TDR is loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded.
Figure 28-12. Peripheral Deselection CSAAT = 0 TDRE NPCS[0..3] CSAAT = 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR 28.7.3.
When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register.
28.8 Serial Peripheral Interface (SPI) User Interface Table 28-5.
28.8.1 SPI Control Register Name: SPI_CR Address: 0xFFFA4000 (0), 0xFFFA8000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI.
28.8.2 SPI Mode Register Name: SPI_MR Address: 0xFFFA4004 (0), 0xFFFA8004 (1) Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – – MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode. • PS: Peripheral Select 0: Fixed Peripheral Select. 1: Variable Peripheral Select.
• LLB: Local Loopback Enable 0: Local loopback path disabled. 1: Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
28.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0xFFFA4008 (0), 0xFFFA8008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
28.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0xFFFA400C (0), 0xFFFA800C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
28.8.
• TXBUFE: TX Buffer Empty 0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0: No rising edge detected on NSS pin since last read. 1: A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
28.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0xFFFA4014 (0), 0xFFFA8014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Enables the corresponding interrupt.
28.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0xFFFA4018 (0), 0xFFFA8018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Disables the corresponding interrupt.
28.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0xFFFA401C (0), 0xFFFA801C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
28.8.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Address: 0xFFFA4030 (0), 0xFFFA8030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT – NCPHA CPOL Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
BITS (Continued) Bits Per Transfer 1000 16 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field.
29. Parallel Input/Output Controller (PIO) 29.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
29.2 Block Diagram Figure 29-1. Block Diagram PIO Controller AIC PMC PIO Interrupt PIO Clock Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Figure 29-2.
29.3 Product Dependencies 29.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
29.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 29-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 29-3.
29.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 29.4.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 29.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted.
Figure 29-6. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 29.4.11 Write Protected Registers To prevent any single software error that may corrupt the PIO behavior, the registers listed below can be writeprotected by setting the WPEN bit in the PIO Write Protect Mode Register (PIO_WPMR).
29.4.12 Programmable I/O Delays The PIO interface consists of a series of signals driven by peripherals or directly by software. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, PIO_DELAY.
29.5 I/O Lines Programming Example The programing example as shown in Table 29-1 below is used to define the following configuration.
29.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 29-2.
Table 29-2.
29.6.1 PIO Enable Register Name: PIO_PER Address: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD), 0xFFFFFA00 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: PIO Enable 0: No effect.
29.6.2 PIO Disable Register Name: PIO_PDR Address: 0xFFFFF204 (PIOA), 0xFFFFF404 (PIOB), 0xFFFFF604 (PIOC), 0xFFFFF804 (PIOD), 0xFFFFFA04 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: PIO Disable 0: No effect.
29.6.
29.6.4 PIO Output Enable Register Name: PIO_OER Address: 0xFFFFF210 (PIOA), 0xFFFFF410 (PIOB), 0xFFFFF610 (PIOC), 0xFFFFF810 (PIOD), 0xFFFFFA10 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Enable 0: No effect.
29.6.5 PIO Output Disable Register Name: PIO_ODR Address: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD), 0xFFFFFA14 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Disable 0: No effect.
29.6.6 PIO Output Status Register Name: PIO_OSR Address: 0xFFFFF218 (PIOA), 0xFFFFF418 (PIOB), 0xFFFFF618 (PIOC), 0xFFFFF818 (PIOD), 0xFFFFFA18 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Status 0: The I/O line is a pure input.
29.6.7 PIO Input Filter Enable Register Name: PIO_IFER Address: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD), 0xFFFFFA20 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Filter Enable 0: No effect.
29.6.8 PIO Input Filter Disable Register Name: PIO_IFDR Address: 0xFFFFF224 (PIOA), 0xFFFFF424 (PIOB), 0xFFFFF624 (PIOC), 0xFFFFF824 (PIOD), 0xFFFFFA24 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Filter Disable 0: No effect.
29.6.
29.6.10 PIO Set Output Data Register Name: PIO_SODR Address: 0xFFFFF230 (PIOA), 0xFFFFF430 (PIOB), 0xFFFFF630 (PIOC), 0xFFFFF830 (PIOD), 0xFFFFFA30 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Set Output Data 0: No effect.
29.6.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD), 0xFFFFFA34 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Clear Output Data 0: No effect.
29.6.
29.6.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0xFFFFF23C (PIOA), 0xFFFFF43C (PIOB), 0xFFFFF63C (PIOC), 0xFFFFF83C (PIOD), 0xFFFFFA3C (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Data Status 0: The I/O line is at level 0.
29.6.14 PIO Interrupt Enable Register Name: PIO_IER Address: 0xFFFFF240 (PIOA), 0xFFFFF440 (PIOB), 0xFFFFF640 (PIOC), 0xFFFFF840 (PIOD), 0xFFFFFA40 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Enable 0: No effect.
29.6.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0xFFFFF244 (PIOA), 0xFFFFF444 (PIOB), 0xFFFFF644 (PIOC), 0xFFFFF844 (PIOD), 0xFFFFFA44 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Disable 0: No effect.
29.6.
29.6.
29.6.18 PIO Multi-driver Enable Register Name: PIO_MDER Address: 0xFFFFF250 (PIOA), 0xFFFFF450 (PIOB), 0xFFFFF650 (PIOC), 0xFFFFF850 (PIOD), 0xFFFFFA50 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Multi Drive Enable 0: No effect.
29.6.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD), 0xFFFFFA54 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Multi Drive Disable 0: No effect.
29.6.
29.6.21 PIO Pull Up Disable Register Name: PIO_PUDR Address: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD), 0xFFFFFA60 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Pull Up Disable 0: No effect.
29.6.22 PIO Pull Up Enable Register Name: PIO_PUER Address: 0xFFFFF264 (PIOA), 0xFFFFF464 (PIOB), 0xFFFFF664 (PIOC), 0xFFFFF864 (PIOD), 0xFFFFFA64 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Pull Up Enable 0: No effect.
29.6.
29.6.24 PIO Peripheral A Select Register Name: PIO_ASR Address: 0xFFFFF270 (PIOA), 0xFFFFF470 (PIOB), 0xFFFFF670 (PIOC), 0xFFFFF870 (PIOD), 0xFFFFFA70 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Peripheral A Select 0: No effect.
29.6.25 PIO Peripheral B Select Register Name: PIO_BSR Address: 0xFFFFF274 (PIOA), 0xFFFFF474 (PIOB), 0xFFFFF674 (PIOC), 0xFFFFF874 (PIOD), 0xFFFFFA74 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Peripheral B Select 0: No effect.
29.6.
29.6.27 PIO Output Write Enable Register Name: PIO_OWER Address: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD), 0xFFFFFAA0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Write Enable 0: No effect.
29.6.28 PIO Output Write Disable Register Name: PIO_OWDR Address: 0xFFFFF2A4 (PIOA), 0xFFFFF4A4 (PIOB), 0xFFFFF6A4 (PIOC), 0xFFFFF8A4 (PIOD), 0xFFFFFAA4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Write Disable 0: No effect.
29.6.
29.6.30 PIO I/O Delay Register Name: PIO_DELAYxR [x=0..3] Address: 0xFFFFF2C0 (PIOA), 0xFFFFF4C0 (PIOB), 0xFFFFF6C0 (PIOC), 0xFFFFF8C0 (PIOD), 0xFFFFFAC0 (PIOE) Access: Read/Write 31 30 29 28 27 26 Delay7 23 22 21 20 19 18 Delay5 15 14 13 6 24 17 16 9 8 1 0 Delay4 12 11 10 Delay3 7 25 Delay6 Delay2 5 4 Delay1 3 2 Delay0 • Delay x: Gives the number of elements in the delay line associated to pad x.
29.6.31 PIO Write Protect Mode Register Name: PIO_WPMR Address: 0xFFFFF2E4 (PIOA), 0xFFFFF4E4 (PIOB), 0xFFFFF6E4 (PIOC), 0xFFFFF8E4 (PIOD), 0xFFFFFAE4 (PIOE) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
29.6.32 PIO Write Protect Status Register Name: PIO_WPSR Address: 0xFFFFF2E8 (PIOA), 0xFFFFF4E8 (PIOB), 0xFFFFF6E8 (PIOC), 0xFFFFF8E8 (PIOD), 0xFFFFFAE8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Enable 0: No Write Protect Violation has occurred since the last read of the PIO_WPSR.
30. Two-wire Interface (TWI) 30.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real-time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
30.3 List of Abbreviations Table 30-2. 30.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 30-1.
30.5 Application Block Diagram Figure 30-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.5.1 I/O Lines Description Table 30-3. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 30.6 Product Dependencies 30.6.
30.6.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. Table 30-5. Peripheral IDs Instance ID TWI0 12 TWI1 13 30.7 Functional Description 30.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 30-4).
30.7.3 Master Mode 30.7.3.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 30.7.3.2 Application Block Diagram Figure 30-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.7.3.
Figure 30-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 30-7. Master Write with Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Figure 30-8.
30.7.3.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge.
30.7.3.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
Figure 30-15.
Figure 30-16.
Figure 30-17.
Figure 30-18.
Figure 30-19.
Figure 30-20.
30.7.4 Multi-master Mode 30.7.4.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 30-21. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 30-22.
Figure 30-23.
30.7.5 Slave Mode 30.7.5.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 30.7.5.2 Application Block Diagram Figure 30-24.
Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 30-26 on page 518.
Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 30-28 describes the clock synchronization in Read mode. Figure 30-28.
Figure 30-29. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full S TWD SADR W A DATA0 A DATA1 TWI_RHR A NA DATA2 DATA1 DATA0 is not read in the RHR S ADR DATA2 SCLWS SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD As soon as a START is detected TXCOMP Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2.
Figure 30-31. Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR TWD S SADR W A DATA0 TWI_RHR A DATA1 DATA0 A Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP Notes: Read TWI_RHR Cleared after read As soon as a START is detected 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2.
Figure 30-32.
30.8 Two-wire Interface (TWI) User Interface Table 30-6.
30.8.1 TWI Control Register Name: TWI_CR Address: 0xFFF84000 (0), 0xFFF88000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.
• SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0: No effect. 1: If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset.
30.8.
30.8.3 TWI Slave Mode Register Name: TWI_SMR Address: 0xFFF84008 (0), 0xFFF88008 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call.
30.8.4 TWI Internal Address Register Name: TWI_IADR Address: 0xFFF8400C (0), 0xFFF8800C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
30.8.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0xFFF84010 (0), 0xFFF88010 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
30.8.6 TWI Status Register Name: TWI_SR Address: 0xFFF84020 (0), 0xFFF88020 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 30-25 on page 517, Figure 30-28 on page 519, Figure 30-30 on page 520 and Figure 30-31 on page 521. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
30.8.
30.8.
30.8.
30.8.
30.8.
31. Timer Counter (TC) 31.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
31.3 Block Diagram Figure 31-1.
31.5 Product Dependencies 31.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 31-4. 31.5.
31.6 Functional Description 31.6.1 TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 31-5 on page 553. 31.6.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
Figure 31-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 31-3.
31.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 31-4. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
The following triggers are common to both modes: Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 31-5.
31.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TIOB MTIOB TIOA MTIOA Figur
31.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 31-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 31-8. RC Compare cannot be programmed to generate a trigger in this configuration.
31.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 31-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 31-10.
31.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 31-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 31-12.
31.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 31-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 31-14.
31.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
31.7 Timer Counter (TC) User Interface Table 31-5.
31.7.1 TC Block Control Register Name: TC_BCR Address: 0xFFF7C0C0 (0), 0xFFFD40C0 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
31.7.
31.7.3 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0xFFF7C000 (0)[0], 0xFFF7C040 (0)[1], 0xFFF7C080 (0)[2], 0xFFFD4000 (1)[0], 0xFFFD4040 (1)[1], 0xFFFD4080 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0: No effect.
31.7.4 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
• LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock.
31.7.5 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..
• EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
• ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BEEV
• BSWTRG: Software Trigger Effect on TIOB BSWTRG 562 Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM9G45 [DATASHEET] Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
31.7.6 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0xFFF7C010 (0)[0], 0xFFF7C050 (0)[1], 0xFFF7C090 (0)[2], 0xFFFD4010 (1)[0], 0xFFFD4050 (1)[1], 0xFFFD4090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
31.7.7 TC Register A Name: TC_RAx [x=0..2] Address: 0xFFF7C014 (0)[0], 0xFFF7C054 (0)[1], 0xFFF7C094 (0)[2], 0xFFFD4014 (1)[0], 0xFFFD4054 (1)[1], 0xFFFD4094 (1)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
31.7.8 TC Register B Name: TC_RBx [x=0..2] Address: 0xFFF7C018 (0)[0], 0xFFF7C058 (0)[1], 0xFFF7C098 (0)[2], 0xFFFD4018 (1)[0], 0xFFFD4058 (1)[1], 0xFFFD4098 (1)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
31.7.9 TC Register C Name: TC_RCx [x=0..2] Address: 0xFFF7C01C (0)[0], 0xFFF7C05C (0)[1], 0xFFF7C09C (0)[2], 0xFFFD401C (1)[0], 0xFFFD405C (1)[1], 0xFFFD409C (1)[2] Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
31.7.10 TC Status Register Name: TC_SRx [x=0..
• ETRGS: External Trigger Status 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
31.7.11 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0xFFF7C024 (0)[0], 0xFFF7C064 (0)[1], 0xFFF7C0A4 (0)[2], 0xFFFD4024 (1)[0], 0xFFFD4064 (1)[1], 0xFFFD40A4 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect.
31.7.12 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address 0xFFF7C028 (0)[0], 0xFFF7C068 (0)[1], 0xFFF7C0A8 (0)[2], 0xFFFD4028 (1)[0], 0xFFFD4068 (1)[1], 0xFFFD40A8 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect.
31.7.13 TC Interrupt Mask Register Name: TC_IMRx [x=0..
32. Universal Synchronous Asynchronous Receiver Transmitter (USART) 32.1 Description The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
32.3 Block Diagram Figure 32-1. USART Block Diagram Peripheral DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS PMC MCK DIV SCK Baud Rate Generator MCK/DIV User Interface SLCK APB Table 32-1.
32.4 Application Block Diagram Figure 32-2. Application Block Diagram IrLAP PPP Serial Driver Field Bus Driver EMV Driver IrDA Driver SPI Driver USART 32.5 RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers SPI Bus I/O Lines Description Table 32-2.
32.6 Product Dependencies 32.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
32.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Inter-rupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 32-4.
32.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication ̶ MSB- or LSB-first 1, 1.
32.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
Baud Rate Calculation Example Table 32-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 32-5. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.
32.7.1.2 Fractional Baud Rate in Asynchronous Mode The baud rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the reference source clock.
32.7.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: B is the bit rate Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 32-6. Table 32-6.
Figure 32-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 32.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
Figure 32-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character.
Figure 32-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter 32.7.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 3214. The sample pulse rejection mechanism applies.
When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.
Figure 32-18. ASK Modulator Output 1 0 0 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 32-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 32.7.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock.
Figure 32-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 32.7.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 591. Even and odd parity bit generation and error detection are supported.
Figure 32-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 32.7.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
32.7.3.11 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated.
32.7.3.12 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR).
Table 32-11 gives the maximum time-out period for some standard baud rates. Table 32-11. Maximum Time-out Period Baud Rate (bit/s) Bit time (µs) Time-out (ms) 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 32.7.3.13 Framing Error The receiver is capable of detecting framing errors.
character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1.
32.7.3.16 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 32-27. Figure 32-27. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
32.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 32.7.4.
Figure 32-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 32-32. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 D0 Guard Start Time 2 Bit D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register.
32.7.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). 32.7.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication.
Figure 32-34 shows an example of character transmission. Figure 32-34. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 1 0 1 0 0 1 1 0 1 TXD 3 16 Bit Period Bit Period 32.7.5.2 IrDA Baud Rate Table 32-13 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 32-13.
32.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 32-37. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 32.7.7 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.
Operation in SPI Slave Mode is programmed by writing at 0xF the USART_MODE field in the Mode Register.
Figure 32-38. SPI Transfer Format (CPHA = 1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB 7 8 NSS SPI Master -> RTS SPI Slave -> CTS Figure 32-39.
current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR) is empty, the UNRE (Underrun Error) bit is set.
The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor. 32.7.8.1 Modes of operation The USART can act either as a LIN Master node or as a LIN Slave node.
32.7.8.6 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field.
significant bits of the counter (value divided by 8) gives the new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new fractional part (FP). When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the Baud Rate Generator Register (US_BRGR). Figure 32-43.
If the fractional baud rate is not used, the accuracy of the synchronization becomes much lower. When the counter is stopped, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD). This value is rounded by adding the first insignificant bit.
32.7.8.9 Node Action Depending on the identifier, the node is affected – or not – by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: PUBLISH: the node sends the response. SUBSCRIBE: the node receives the response. IGNORE: the node is not concerned by the response, it does not send and does not receive the response.
32.7.8.10 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1).
32.7.8.12 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to tFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after tFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to tFrame_Maximum.
Inconsistent Synch Field Error This error is generated in Slave node configuration if the Synch Field character received is other than 0x55. Parity Error This error is generated if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). Checksum Error This error is set if the received checksum is wrong. This error can be generated only if the checksum feature is enabled (CHKDIS = 0).
Figure 32-46. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 32-47.
Slave Node Configuration Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration. Write CD and FP in US_BRGR to configure the baud rate. Wait until LINID in US_CSR rises Check LINISFE and LINPE errors Read IDCHR in US_RHR Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in US_LINMR to configure the frame transfer.
Figure 32-50. Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 32-51. Slave Node Configuration, NACT = IGNORE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR LINTC 32.7.8.
Figure 32-52. Master Node with PDC (PDCM = 1) WRITE BUFFER WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC DLC NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE IDENTIFIER APB bus APB bus IDENTIFIER PDC (DMA) USART3 LIN CONTROLLER READ BUFFER PDC (DMA) RXRDY USART3 LIN CONTROLLER RXRDY DATA 0 DATA 0 | | | | TXRDY | | | | DATA N DATA N Figure 32-53.
Slave Node Configuration In this configuration, the PDC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN Mode register (US_LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT = PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE). Figure 32-54.
Table 32-16. Receiver Time-out Programming LIN Specification 2.0 Baud Rate Time-out period US_RTOR.TO 1 000 bit/s 4,000 2 400 bit/s 9,600 9 600 bit/s 4s 38,400 19 200 bit/s 76,800 20 000 bit/s 80,000 1.3 – 25,000 25,000 tbit 32.7.9 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics.
32.7.9.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 32-57. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 32-57. Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 32.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 32-58.
32.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 32-17.
32.8.1 USART Control Register Name: US_CR Address: 0xFFF8C000 (0), 0xFFF90000 (1), 0xFFF94000 (2), 0xFFF98000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select – If USART does not operate in SPI Master Mode (USART_MODE ≠ 0xE): 0: No effect. 1: Drives the pin RTS to 1. – If USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin). • LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. • LINWKUP: Send LIN Wakeup Signal 0: No effect: 1: Sends a wakeup signal on the LIN bus.
32.8.
• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase – If USART does not operate in SPI Mode (USART_MODE is ≠ 0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode. – If USART operates in SPI Mode (USART_MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
• MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated.
32.8.
• LINBE: LIN Bus Error Interrupt Enable • LINISFE: LIN Inconsistent Synch Field Error Interrupt Enable • LINIPE: LIN Identifier Parity Interrupt Enable • LINCE: LIN Checksum Error Interrupt Enable • LINSNRE: LIN Slave Not Responding Error Interrupt Enable SAM9G45 [DATASHEET] Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15 629
32.8.
• LINBE: LIN Bus Error Interrupt Disable • LINISFE: LIN Inconsistent Synch Field Error Interrupt Disable • LINIPE: LIN Identifier Parity Interrupt Disable • LINCE: LIN Checksum Error Interrupt Disable • LINSNRE: LIN Slave Not Responding Error Interrupt Disable SAM9G45 [DATASHEET] Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15 631
32.8.
• LINBE: LIN Bus Error Interrupt Mask • LINISFE: LIN Inconsistent Synch Field Error Interrupt Mask • LINIPE: LIN Identifier Parity Interrupt Mask • LINCE: LIN Checksum Error Interrupt Mask • LINSNRE: LIN Slave Not Responding Error Interrupt Mask SAM9G45 [DATASHEET] Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15 633
32.8.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• LINID: LIN Identifier Sent or LIN Identifier Received – If USART operates in LIN Master Mode (USART_MODE = 0xA): 0: No LIN Identifier has been sent since the last RSTSTA. 1:At least one LIN Identifier has been sent since the last RSTSTA. – If USART operates in LIN Slave Mode (USART_MODE = 0xB): 0: No LIN Identifier has been received since the last RSTSTA. 1:At least one LIN Identifier has been received since the last RSTSTA • LINTC: LIN Transfer Completed 0: The USART is idle or a LIN transfer is ongoing.
32.8.7 USART Receive Holding Register Name: US_RHR Address: 0xFFF8C018 (0), 0xFFF90018 (1), 0xFFF94018 (2), 0xFFF98018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
32.8.8 USART Transmit Holding Register Name: US_THR Address: 0xFFF8C01C (0), 0xFFF9001C (1), 0xFFF9401C (2), 0xFFF9801C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
32.8.
32.8.10 USART Receiver Time-out Register Name: US_RTOR Address: 0xFFF8C024 (0), 0xFFF90024 (1), 0xFFF94024 (2), 0xFFF98024 (3) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1–131071: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
32.8.11 USART Transmitter Timeguard Register Name: US_TTGR Address: 0xFFF8C028 (0), 0xFFF90028 (1), 0xFFF94028 (2), 0xFFF98028 (3) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
32.8.12 USART FI DI RATIO Register Name: US_FIDI Address: 0xFFF8C040 (0), 0xFFF90040 (1), 0xFFF94040 (2), 0xFFF98040 (3) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
32.8.13 USART Number of Errors Register Name: US_NER Address: 0xFFF8C044 (0), 0xFFF90044 (1), 0xFFF94044 (2), 0xFFF98044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
32.8.14 USART IrDA FILTER Register Name: US_IF Address: 0xFFF8C04C (0), 0xFFF9004C (1), 0xFFF9404C (2), 0xFFF9804C (3) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
32.8.
• DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.
32.8.16 USART3 LIN Mode Register Name: US_LINMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • NACT: LIN Node Action NACT Mode Description 0 0 PUBLISH: The USART transmits the response. 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response.
• WKUPTYP: Wakeup Signal Type 0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. • DLC: Data Length Control 0–255: Defines the response data length if DLM = 0,in that case the response data length is equal to DLC+1 bytes. • PDCM: PDC Mode 0: The LIN mode register US_LINMR is not written by the PDC. 1: The LIN mode register US_LINMR (excepting that flag) is written by the PDC.
32.8.17 USART3 LIN Identifier Register Name: US_LINIR Access: Read/Write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If USART_MODE = 0xA (Master node configuration): IDCHR is Read/Write and its value is the Identifier character to be transmitted.
33. Synchronous Serial Controller (SSC) 33.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
33.3 Block Diagram Figure 33-1.
Figure 33-2. Block Diagram (with DMA) System Bus APB Bridge DMA Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 33.4 Application Block Diagram Figure 33-3.
33.5 Pin Name List Table 33-1. 33.6 I/O Lines Description Pin Name Pin Description Type RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output Product Dependencies 33.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
33.6.3 Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and Table 33-3. Peripheral IDs Instance ID SSC0 16 SSC1 17 unmasked SSC interrupt will assert the SSC interrupt line.
33.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
33.7.1 Clock Management The transmitter clock can be generated by: an external clock received on the TK I/O pad the receiver clock the internal clock divider The receiver clock can be generated by: an external clock received on the RK I/O pad the transmitter clock the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
33.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR.
33.7.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 33-9. Transmitter Block Diagram SSC_CRTXEN SSC_SRTXEN TXEN SSC_CRTXDIS SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_RCMR.START SSC_TCMR.START SSC_TFMR.DATNB SSC_TFMR.DATDEF SSC_TFMR.
Figure 33-10. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN Start Selector RF RC0R SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start RX Controller RD Receive Shift Register SSC_RCMR.STTDLY != 0 load SSC_RSHR load SSC_RFMR.FSLEN SSC_RHR Receiver Clock SSC_RFMR.DATLEN RX Controller counter reached STTDLY 33.7.
Figure 33-11. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 33-12.
33.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported.
Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. 33.7.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR).
Figure 33-14. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD TF/RF (1) FSLEN TD (If FSDEN = 1) Sync Data Data Data From SSC_THR From SSC_THR Default Data Data TD (If FSDEN = 0) RD Default From SSC_TSHR FromDATDEF From SSC_THR From DATDEF Sync Data Ignored FromDATDEF From DATDEF Ignored Data To SSC_RHR To SSC_RHR DATLEN DATLEN STTDLY Sync Data Default From SSC_THR Data To SSC_RSHR Default Sync Data DATNB Note: 1.
33.7.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event.
33.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 33-19. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB Right Channel Left Channel Figure 33-20.
Figure 33-21.
33.9 Synchronous Serial Controller (SSC) User Interface Table 33-5.
33.9.1 SSC Control Register Name: SSC_CR Address: 0xFFF9C000 (0), 0xFFFA0000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive.
33.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0xFFF9C004 (0), 0xFFFA0004 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any other value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
33.9.
• START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
33.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0xFFF9C014 (0), 0xFFFA0014 (1) Access: Read/Write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT 28 FSLEN_EXT 27 – 26 – 25 – 24 FSEDGE 23 – 22 21 FSOS 20 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 MSBF 6 – 5 LOOP 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
• FSOS: Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Input-only Reserved • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
33.9.
• START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
33.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0xFFF9C01C (0), 0xFFFA001C (1) Access: Read/Write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT 28 FSLEN_EXT 27 – 26 – 25 – 24 FSEDGE 23 FSDEN 22 21 FSOS 20 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 MSBF 6 – 5 DATDEF 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
• FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Reserved • FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal.
33.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0xFFF9C020 (0), 0xFFFA0020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
33.9.8 SSC Transmit Holding Register Name: SSC_THR Address: 0xFFF9C024 (0), 0xFFFA0024 (1) Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
33.9.
33.9.
33.9.
33.9.
33.9.13 SSC Status Register Name: SSC_SR Address: 0xFFF9C040 (0), 0xFFFA0040 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty.
• RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register.
33.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0xFFF9C044 (0), 0xFFFA0044 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect.
• RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
33.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0xFFF9C048 (0), 0xFFFA0048 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect.
• RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
33.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0xFFF9C04C (0), 0xFFFA004C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled.
• RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled.
34. Ethernet MAC 10/100 (EMAC) 34.1 Description The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.
34.3 Block Diagram Figure 34-1.
34.4 Functional Description The MACB has several clock domains: System bus clock (AHB and APB): DMA and register blocks Transmit clock: transmit block Receive clock: receive and address checker block The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps). Figure 34-1 illustrates the different blocks of the EMAC module.
Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words. Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes) of data.
Table 34-1. Receive Buffer Descriptor Entry (Continued) Bit 19:17 Function VLAN priority (only valid if bit 21 is set) 16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set) 15 End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. 14 Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt.
To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-buffer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad.
After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen.
34.4.6 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame’s destination address. In this implementation of the EMAC, the frame’s source address is not checked.
34.4.7 Broadcast Address The broadcast address of 0xFFFFFFFFFFFF is recognized if the ‘no broadcast’ bit in the network configuration register is zero. 34.4.8 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.
34.4.11 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 34-4. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame.
The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake-on-LAN target address value does not cause an ARP request event, even if matched by the frame.
Table 34-5.
Figure 34-2. Receive Buffer List Receive Buffer 0 Receive Buffer Queue Pointer (MAC Register) Receive Buffer 1 Receive Buffer N Receive Buffer Descriptor List (In memory) (In memory) To create the list of buffers: 1. Allocate a number (n) of buffers of 128 bytes in system memory. 2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and create n entries in this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0. 3.
34.5.1.5 Interrupts There are 15 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt. Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the AIC programmer datasheet). To ascertain which interrupt has been generated, read the interrupt status register. Note that this register clears itself when read.
34.6 Ethernet MAC 10/100 (EMAC) User Interface Table 34-6.
Table 34-6.
34.6.1 Network Control Register Name: EMAC_NCR Address: 0xFFFBC000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
• TSTART: Start transmission Writing one to this bit starts transmission. • THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
34.6.2 Network Configuration Register Name: EMAC_NCFG Address: 0xFFFBC004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 – 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
• CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations) . CLK MDC 00 MCK divided by 8 (MCK up to 20 MHz) 01 MCK divided by 16 (MCK up to 40 MHz) 10 MCK divided by 32 (MCK up to 80 MHz) 11 MCK divided by 64 (MCK up to 160 MHz) • RTY: Retry test Must be set to zero for normal operation.
34.6.3 Network Status Register Name: EMAC_NSR Address: 0xFFFBC008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0: The PHY logic is running. 1: The PHY management logic is idle (i.e., has completed).
34.6.4 Transmit Status Register Name: EMAC_TSR Address: 0xFFFBC014 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
34.6.5 Receive Buffer Queue Pointer Register Name: EMAC_RBQP Address: 0xFFFBC018 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
34.6.6 Transmit Buffer Queue Pointer Register Name: EMAC_TBQP Address: 0xFFFBC01C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
34.6.7 Receive Status Register Name: EMAC_RSR Address: 0xFFFBC020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
34.6.8 Interrupt Status Register Name: EMAC_ISR Address: 0xFFFBC024 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
• PFR: Pause Frame Received Indicates a valid pause has been received. Cleared on a read. • PTZ: Pause Time Zero • Set when the pause time register, 0x38 decrements to zero. Cleared on a read. • WOL: Wake On LAN Set when a WOL event has been triggered (This flag can be set even if the EMAC is not clocked). Cleared on a read.
34.6.9 Interrupt Enable Register Name: EMAC_IER Address: 0xFFFBC028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt. • RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
• PTZ: Pause Time Zero Enable pause time zero interrupt. • WOL: Wake On LAN Enable Wake On LAN interrupt.
34.6.10 Interrupt Disable Register Name: EMAC_IDR Address: 0xFFFBC02C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt.
• PTZ: Pause Time Zero Disable pause time zero interrupt. • WOL: Wake On LAN Disable Wake On LAN interrupt.
34.6.11 Interrupt Mask Register Name: EMAC_IMR Address: 0xFFFBC030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
• PTZ: Pause Time Zero Pause time zero interrupt masked. • WOL: Wake On LAN Wake On LAN interrupt masked.
34.6.12 PHY Maintenance Register Name: EMAC_MAN Address: 0xFFFBC034 Access: Read/Write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 17 16 PHYA 20 REGA 19 18 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE Must be written to 10. Reads as written.
34.6.13 Pause Time Register Name: EMAC_PTR Address: 0xFFFBC038 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
34.6.14 Hash Register Bottom Name: EMAC_HRB Address: 0xFFFBC090 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Bits 31:0 of the hash address register. See “Hash Addressing” on page 702.
34.6.15 Hash Register Top Name: EMAC_HRT Address: 0xFFFBC094 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Bits 63:32 of the hash address register. See “Hash Addressing” on page 702.
34.6.16 Specific Address 1 Bottom Register Name: EMAC_SA1B Address: 0xFFFBC098 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
34.6.17 Specific Address 1 Top Register Name: EMAC_SA1T Address: 0xFFFBC09C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
34.6.18 Specific Address 2 Bottom Register Name: EMAC_SA2B Address: 0xFFFBC0A0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
34.6.19 Specific Address 2 Top Register Name: EMAC_SA2T Address: 0xFFFBC0A4 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
34.6.20 Specific Address 3 Bottom Register Name: EMAC_SA3B Address: 0xFFFBC0A8 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
34.6.21 Specific Address 3 Top Register Name: EMAC_SA3T Address: 0xFFFBC0AC Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
34.6.22 Specific Address 4 Bottom Register Name: EMAC_SA4B Address: 0xFFFBC0B0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
34.6.23 Specific Address 4 Top Register Name: EMAC_SA4T Address: 0xFFFBC0B4 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
34.6.24 Type ID Checking Register Name: EMAC_TID Address: 0xFFFBC0B8 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID Checking For use in comparisons with received frames TypeID/Length field.
34.6.25 User Input/Output Register Name: EMAC_USRIO Address: 0xFFFBC0C0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CLKEN 0 RMII • RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. • CLKEN When set, this bit enables the transceiver input clock.
34.6.26 Wake-on-LAN Register Name: EMAC_WOL Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 MTI 18 SA1 17 ARP 16 MAG 15 14 13 12 11 10 9 8 3 2 1 0 IP 7 6 5 4 IP • IP: ARP request IP address Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake-on-LAN event. A value of zero does not generate an event, even if this is matched by the received frame.
34.6.27 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers.
34.6.27.1 Pause Frames Received Register Name: EMAC_PFR Address: 0xFFFBC03C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 FROK 7 6 5 4 FROK • FROK: Pause Frames Received OK A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
34.6.27.2 Frames Transmitted OK Register Name: EMAC_FTO Address: 0xFFFBC040 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FTOK 15 14 13 12 FTOK 7 6 5 4 FTOK • FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
34.6.27.3 Single Collision Frames Register Name: EMAC_SCF Address: 0xFFFBC044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun.
34.6.27.4 Multicollision Frames Register Name: EMAC_MCF Address: 0xFFFBC048 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 MCF 7 6 5 4 MCF • MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
34.6.27.5 Frames Received OK Register Name: EMAC_FRO Address: 0xFFFBC04C Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
34.6.27.6 Frames Check Sequence Errors Register Name: EMAC_FCSE Address: 0xFFFBC050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 FCSE • FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register).
34.6.27.
34.6.27.8 Deferred Transmission Frames Register Name: EMAC_DTF Address: 0xFFFBC058 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 DTF 7 6 5 4 DTF • DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission.
34.6.27.9 Late Collisions Register Name: EMAC_LCOL Address: 0xFFFBC05C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
34.6.27.10 Excessive Collisions Register Name: EMAC_ECOL Address: 0xFFFBC060 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 EXCOL • EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
34.6.27.11 Transmit Underrun Errors Register Name: EMAC_TUND Address: 0xFFFBC064 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
34.6.27.
34.6.27.13 Receive Resource Errors Register Name: EMAC_RRE Address: 0xFFFBC06C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.
34.6.27.14 Receive Overrun Errors Register Name: EMAC_ROV Address: 0xFFFBC070 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 ROVR • ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.
34.6.27.15 Receive Symbol Errors Register Name: EMAC_RSE Address: 0xFFFBC074 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
34.6.27.
34.6.27.17 Receive Jabbers Register Name: EMAC_RJA Address: 0xFFFBC07C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.
34.6.27.18 Undersize Frames Register Name: EMAC_USF Address: 0xFFFBC080 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 USF • USF: Undersize Frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
34.6.27.19 SQE Test Errors Register Name: EMAC_STE Address: 0xFFFBC084 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE Test Errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode.
34.6.27.20 Received Length Field Mismatch Register Name: EMAC_RLE Address: 0xFFFBC088 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RLFM • RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field.
35. High Speed Multimedia Card Interface (HSMCI) 35.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
35.3 Block Diagram Figure 35-1. Block Diagram APB Bridge DMAC APB MCCK (1) HSMCI Interface PMC MCK PIO MCCDA (1) MCDA0 (1) MCDA1 (1) MCDA2 (1) MCDA3 (1) Interrupt Control MCDA4 (1) MCDA5 (1) MCDA6 (1) MCDA7 (1) HSMCI Interrupt Notes: 764 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.
35.4 Application Block Diagram Figure 35-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 1011 1213 8 SDCard MMC 35.5 Pin Name List Table 35-1. I/O Lines Description for 8-bit Configuration (2) Pin Name Pin Description Type(1) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA7 Data 0..
35.6 35.6.1 Product Dependencies I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 35-2. 35.6.
35.7 Bus Topology Figure 35-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 1011 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 35-4.
Figure 35-4. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 1011 9 1011 9 1011 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 35-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 35-5. Table 35-5.
SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 35-6. Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI SDCard/SDIO Register (HSMCI_SDCR). Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits.
35.8 High Speed MultiMediaCard Operations After a power-on reset, the cards are initialized by a special message-based High Speed MultiMediaCard bus protocol. Each message is represented by one of the following tokens: Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 35-6 and Table 35-7. Table 35-6. ALL_SEND_CID Command Description CMD Index Type Argument Resp Abbreviation CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Note: Command Description Asks all cards to send their CID numbers on the CMD line 1. bcr means broadcast command with response. Table 35-7.
Figure 35-7. Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? (1) RETURN ERROR Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Notes: 772 1.
35.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the HSMCI_MR, or in the HSMCI Block Register (HSMCI_BLKR).
Figure 35-8.
35.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing nonmultiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI DMA Configuration Register (HSMCI_DMA) enables DMA transfer. The following flowchart (Figure 35-9) shows how to write a single block with or without use of DMA facilities.
Figure 35-9.
Figure 35-10.
4. Program HSMCI_DMA register with the following fields: ̶ OFFSET field with dma_offset. ̶ CHKSIZE is user defined and set according to DMAC_DCSIZE. ̶ DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit was previously set to false. 5. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARGR then HSMCI_CMDR. 6. Program the DMA Controller. a. Read the channel Register to choose an available (disabled) channel. b.
5. Program HSMCI_DMA register with the following fields: ̶ ROPT field is set to 0. ̶ OFFSET field is set to 0. ̶ CHKSIZE is user defined. ̶ DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false. 6. Issue a READ_SINGLE_BLOCK command. 7. Program the DMA controller. a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR. c.
a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR. c. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented. This descriptor is referred to as LLI_W, standing for LLI word oriented transfer. d. The LLI_W.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. e. The LLI_W.
–FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously. o. Program LLI_B.DMAC_CFGx memory location for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. –Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 3. 35.8.7 Wait for XFRDONE in HSMCI_SR. WRITE_MULTIPLE_BLOCK 35.8.7.1 One Block per Descriptor 1. Wait until the current command execution has successfully terminated. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2.
h. Program LLI(n).DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_REP is set to 0. (contiguous memory access at block boundary) –DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. i. If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the start address of LLI(n+1). j.
–BTSIZE is programmed with block_length/4. g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST). –DIF and SIF are set with their respective layer ID.
–SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE field. –BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later. h. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
q. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0. r. Program DMAC_CTRLBx register for channel x with 0, its content is updated with the LLI Fetch operation. s. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of LLI_B(0). t. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 4. Enable DMADONE interrupt in the HSMCI_IER.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. 35.9 i. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to 0. j. Program DMAC_CTRLBx register for channel x with 0.
optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field (IOSPCMD) in the HSMCI Command Register. 35.9.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details).
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism may be used for each error event. The recommended error recovery procedure after a timeout is: Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK (CMD61) response has been received. Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response. Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
35.12 HSMCI Transfer Done Timings 35.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 35.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 35-11. Figure 35-11. XFRDONE During a Read Access CMD line HSMCI read CMD Card response The CMDRDY flag is released 8 tbit after the end of the card response. CMDRDY flag Data Last Block 1st Block Not busy flag XFRDONE flag 35.12.
35.13 Write Protection Registers To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register” (HSMCI_WPMR).
35.14 High Speed MultiMediaCard Interface (HSMCI) User Interface Table 35-8.
35.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0xFFF80000 (0), 0xFFFD0000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0: No effect.
35.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0xFFF80004 (0), 0xFFFD0004 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 BLKLEN 23 22 21 20 BLKLEN 15 – 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 818.
• PADV: Padding Value 0: 0x00 value is used when padding data in write transfer. 1: 0xFF value is used when padding data in write transfer. PADV may be only in manual transfer. • BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR). Bits 16 and 17 must be set to 0 if FBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used.
35.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0xFFF80008 (0), 0xFFFD0008 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 818.
35.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0xFFF8000C (0), 0xFFFD000C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 818. • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
35.14.
35.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0xFFF80014 (0), 0xFFFD0014 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
• OPDCMD: Open Drain Command 0 (PUSHPULL): Push pull command. 1 (OPENDRAIN): Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5): 5-cycle max latency. 1 (64): 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA No data transfer 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 – Reserved • TRDIR: Transfer Direction 0 (WRITE): Write. 1 (READ): Read.
35.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0xFFF80018 (0), 0xFFFD0018 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
35.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0xFFF8001C (0), 0xFFFD001C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 818.
35.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0xFFF80020 (0), 0xFFFD0020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
35.14.
35.14.
35.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0xFFF80040 (0), 0xFFFD0040 (1) Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 – 14 – 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent.
The NOTBUSY flag allows to deal with these different states. 0: The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1: The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
• DCRCE: Data CRC Error 0: No error. 1: A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR. • DTOE: Data Time-out Error 0: No error. 1: The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR. • CSTOE: Completion Signal Time-out Error 0: No error. 1: The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR. Cleared by reading in the HSMCI_SR.
• UNRE: Underrun 0: No error. 1: At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1. When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
35.14.
• FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
35.14.
• FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
35.14.
• FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
35.14.16 HSMCI DMA Configuration Register Name: HSMCI_DMA Address: 0xFFF80050 (0), 0xFFFD0050 (1) Access: Read/Write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 ROPT 11 – 10 – 9 – 8 DMAEN 7 – 6 – 5 4 3 – 2 – 1 CHKSIZE 0 OFFSET This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 818.
35.14.17 HSMCI Configuration Register Name: HSMCI_CFG Address: 0xFFF80054 (0), 0xFFFD0054 (1) Access: Read/Write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 818.
35.14.18 HSMCI Write Protect Mode Register Name: HSMCI_WPMR Address: 0xFFF800E4 (0), 0xFFFD00E4 (1) Access: Read/Write 31 30 29 28 27 WP_KEY (0x4D => “M”) 26 25 24 23 22 21 20 19 WP_KEY (0x43 => C”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 – 6 – 5 – 2 – 1 – 0 WP_EN 4 – 3 – • WP_EN: Write Protection Enable 0: Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI” in ASCII).
35.14.
35.14.20 HSMCI FIFOx Memory Aperture Name: HSMCI_FIFOx[x=0..
36. USB High Speed Host Port (UHPHS) 36.1 Description The USB High Speed Host Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface). 36.2 Embedded Characteristics The SAM9G45 features USB communication ports as follows: 2 Ports USB Host full speed OHCI and High speed EHCI 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver.
The USB Host Port controller is fully compliant with the Open HCI specification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification available on www.hp.com. The standard OHCI USB stack driver can be easily ported to Atmel’s architecture, in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user’s application.
The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller.
For OHCI Full-speed operations only, the user has to perform the following: Enable UHP peripheral clock in PMC_PCER Select PLLACK as Input clock of OHCI part (USBS bit in PMC_USB register) Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV value is to calculated regarding the PLLACK value and USB Full-speed accuracy. Enable the OHCI clocks with UHP bit in PMC_SCER Figure 36-3.
36.6 Typical Connection Figure 36-4. Board Schematic to Interface UHP High-speed Device Controller PIO (VBUS DETECT) 15k Ω (1) "A" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND HHSDM 39 ± 5% Ω HFSDM 3 4 (1) 22k Ω Shell = Shield HHSDP CRPB 1 2 39 ± 5% Ω CRPB: 1µF to 10µF HFSDP 6K8 ± 1% Ω VBG 10 pF GNDUTMI Note: 1. The values shown on the 22k Ω and 15k Ω resistors are only valid for 3v3 supplied PIOs.
37. USB High Speed Device Port (UDPHS) 37.1 Description The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a dual-port RAM used to store the current data payload.
Table 37-1. UDPHS Endpoint Description Endpoint # Mnemonic Nb Bank DMA High BandWidth Max. Endpoint Size Endpoint Type 0 EPT_0 1 N N 64 Control 1 EPT_1 2 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt 2 EPT_2 2 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt 3 EPT_3 3 Y N 1024 Ctrl/Bulk/Iso(1)/Interrupt 4 EPT_4 3 Y N 1024 Ctrl/Bulk/Iso(1)/Interrupt 5 EPT_5 3 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt 6 EPT_6 3 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt Note: 1.
37.3 Block Diagram Figure 37-2. Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready DMA AHB0 APB bus Master AHB Multiplexer Slave Local AHB Slave interface EPT Alloc 32 bits DPRAM System Clock Domain PMC 828 UTMI USB2.
37.4 Typical Connection Figure 37-3. Board Schematic PIO (VBUS DETECT) 15k Ω (1) "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 2 3 4 DHSDM 39 ± 5% Ω DFSDM Shell = Shield (1) 22k Ω CRPB DHSDP 39 ± 5% Ω CRPB:1µF to 10µF DFSDP 6K8 ± 1% Ω VBG 10 pF GNDUTMI Note: 1. The values shown on the 22kΩ and 15kΩ resistors are only valid with 3V3 supplied PIOs.
37.5 Functional Description 37.5.1 USB V2.0 High Speed Device Port Introduction The USB V2.0 High Speed Device Port provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB Device through a set of communication flows. 37.5.2 USB V2.
37.5.3 USB Transfer Event Definitions A transfer is composed of one or several transactions. Table 37-3.
Figure 37-4. Control Read and Write Sequences Setup Stage Control Write Setup TX Data Stage Data OUT TX Setup Stage Control Read No Data Control Setup TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Data IN TX Status IN TX Status Stage Status OUT TX A status IN or OUT transaction is identical to a data IN or OUT transaction. 37.5.
The size of the DPRAM is 4 Kbyte. The DPR is shared by all active endpoints. The memory size required by the active endpoints must not exceed the size of the DPRAM. SIZE_DPRAM = SIZE _EPT0 + NB_BANK_EPT1 x SIZE_EPT1 + NB_BANK_EPT2 x SIZE_EPT2 + NB_BANK_EPT3 x SIZE_EPT3 + NB_BANK_EPT4 x SIZE_EPT4 + NB_BANK_EPT5 x SIZE_EPT5 + NB_BANK_EPT6 x SIZE_EPT6 +... (refer to Section 37.6.
Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Register) for Bulk IN endpoint type follow below. With DMA ̶ ̶ AUTO_VALID: Automatically validate the packet and switch to the next bank. EPT_ENABL: Enable endpoint. Without DMA: ̶ TX_BK_RDY: An interrupt is generated after each transmission. ̶ EPT_ENABL: Enable endpoint. Configuration examples of Bulk OUT endpoint type follow below. With DMA ̶ AUTO_VALID: Automatically validate the packet and switch to the next bank.
Figure 37-6. Example of DMA Chained List: Transfer Descriptor UDPHS Registers (Current Transfer Descriptor) Next Descriptor Address DMA Channel Address Transfer Descriptor UDPHS Next Descriptor DMA Channel Control Next Descriptor Address DMA Channel Address DMA Channel Address Transfer Descriptor DMA Channel Control Next Descriptor Address DMA Channel Control DMA Channel Address DMA Channel Control Null Memory Area Data Buff 1 Data Buff 2 Data Buff 3 37.5.
37.5.8 Handling Transactions with USB V2.0 Device Peripheral 37.5.8.1 Setup Transaction The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the UDPHS accepts the next packets sent over the device endpoint.
37.5.8.3 Data IN Bulk IN or Interrupt IN Data IN packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel.
Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3.
Figure 37-8.
Figure 37-10. Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Token IN Device Sends a Status OUT to Host ACK Data IN Token OUT Data OUT (ZLP) ACK Token OUT Data OUT (ZLP) ACK Interrupt Pending RX_BK_RDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Note: Cleared by Firmware A NAK handshake is always generated at the first status stage token. Figure 37-11.
Figure 37-12.
A response should be made to the first token IN recognized inside a microframe under the following conditions: If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end.
Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device) Algorithm Description for Each Packet: The application enables an interrupt on RX_BK_RDY. When an interrupt on RX_BK_RDY is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received. The application reads the BYTE_COUNT bytes from the endpoint. The application clears RX_BK_RDY.
Figure 37-13.
High Bandwidth Isochronous Endpoint OUT Figure 37-15. Bank Management, Example of Three Transactions per Microframe USB bus Transactions MDATA0 MDATA1 DATA2 t=0 RX_BK_RDY Microcontroller FIFO (DPR) Access MDATA0 Read Bank 2 DATA2 USB line t = 125 µs t = 52.5 µs (40% of 125 µs) Read Bank 1 MDATA1 RX_BK_RDY Read Bank 3 Read Bank 1 USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe.
If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RX_BK_RDY flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null. The FRCESTALL command bit is unused for an isochonous endpoint. Otherwise, payload data is written in the endpoint, the RX_BK_RDY interrupt is generated and the BYTE_COUNT in UDPHS_EPTSTAx register is updated. 37.5.8.
37.5.10 USB V2.0 High Speed Global Interrupt Interrupts are defined in Section 37.6.3 ”UDPHS Interrupt Enable Register” (UDPHS_IEN) and in Section 37.6.4 ”UDPHS Interrupt Status Register” (UDPHS_INTSTA). 37.5.11 Endpoint Interrupts Interrupts are enabled in UDPHS_IEN (see Section 37.6.3 ”UDPHS Interrupt Enable Register”) and individually masked in UDPHS_EPTCTLENBx (see Section 37.6.9 ”UDPHS Endpoint Control Enable Register”). Table 37-4.
Figure 37-18.
37.5.12 Power Modes 37.5.12.1 Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 37-19.
37.5.12.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. 37.5.12.
In this state bus powered devices must drain less than 500 µA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected. 37.5.12.
37.6 USB High Speed Device Port (UDPHS) User Interface Table 37-5.
37.6.1 UDPHS Control Register Name: UDPHS_CTRL Address: 0xFFF78000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 PULLD_DIS 10 REWAKEUP 9 DETACH 8 EN_UDPHS 7 FADDR_EN 6 5 4 3 DEV_ADDR 2 1 0 • DEV_ADDR: UDPHS Address Read: This field contains the default address (0) after power-up or UDPHS bus reset.
• DETACH: Detach Command Read: 0: UDPHS is attached. 1: UDPHS is detached, UTMI transceiver is suspended. Write: 0: Pull up the DP line (attach command). 1: Simulate a detach on the UDPHS line and force the UTMI transceiver into suspend state (Suspend M = 0). (See PULLD_DIS description below.) • REWAKEUP: Send Remote Wake Up Read: 0: Remote Wake Up is disabled. 1: Remote Wake Up is enabled. Write: 0: No effect. 1: Force an external interrupt on the UDPHS controller for Remote Wake UP purposes.
37.6.2 UDPHS Frame Number Register Name: UDPHS_FNUM Address: 0xFFF78004 Access: Read 31 FNUM_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 FRAME_NUMBER 9 8 7 6 5 FRAME_NUMBER 4 3 1 MICRO_FRAME_NUM 0 2 • MICRO_FRAME_NUM: Microframe Number Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8).
37.6.3 UDPHS Interrupt Enable Register Name: UDPHS_IEN Address: 0xFFF78010 Access: Read/Write 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Enable Read: 0: Suspend Interrupt is disabled. 1: Suspend Interrupt is enabled.
• ENDRESET: End Of Reset Interrupt Enable Read: 0: End Of Reset Interrupt is disabled. 1: End Of Reset Interrupt is enabled. Write: 0: Disable End Of Reset Interrupt. 1: Enable End Of Reset Interrupt. Automatically enabled after USB reset. • WAKE_UP: Wake Up CPU Interrupt Enable Read: 0: Wake Up CPU Interrupt is disabled. 1: Wake Up CPU Interrupt is enabled. Write 0: Disable Wake Up CPU Interrupt. 1: Enable Wake Up CPU Interrupt.
• DMA_x: DMA Channel x Interrupt Enable Read: 0: The interrupts for this channel are disabled. 1: The interrupts for this channel are enabled. Write: 0: Disable the interrupts for this channel. 1: Enable the interrupts for this channel.
37.6.4 UDPHS Interrupt Status Register Name: UDPHS_INTSTA Address: 0xFFF78014 Access: Read-only 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 SPEED • SPEED: Speed Status 0: Reset by hardware when the hardware is in Full Speed mode.
• WAKE_UP: Wake Up CPU Interrupt 0: Cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation.
37.6.5 UDPHS Clear Interrupt Register Name: UDPHS_CLRINT Address: 0xFFF78018 Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Clear 0: No effect. 1: Clear the DET_SUSPD bit in UDPHS_INTSTA. • MICRO_SOF: Micro Start Of Frame Interrupt Clear 0: No effect.
37.6.6 UDPHS Endpoints Reset Register Name: UDPHS_EPTRST Address: 0xFFF7801C Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 EPT_6 5 EPT_5 4 EPT_4 3 EPT_3 2 EPT_2 1 EPT_1 0 EPT_0 • EPT_x: Endpoint x Reset 0: No effect. 1: Reset the Endpointx state. Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field.
37.6.
• OPMODE2: OpMode2 Read and write: 0: No effect. 1: Set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding. Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host.
37.6.8 UDPHS Endpoint Configuration Register Name: UDPHS_EPTCFGx [x=0..
• EPT_TYPE: Endpoint Type Read and write: Set this field according to the endpoint type (see Section 37.5.5 ”Endpoint Configuration”). (Endpoint 0 should always be configured as control) Endpoint Type 00 Control endpoint 01 Isochronous endpoint 10 Bulk endpoint 11 Interrupt endpoint • BK_NUMBER: Number of Banks Read and write: Set this field according to the endpoint’s number of banks (see Section 37.5.5 ”Endpoint Configuration”).
37.6.9 UDPHS Endpoint Control Enable Register Name: UDPHS_EPTCTLENBx [x=0..
• ERR_OVFLW: Overflow Error Interrupt Enable 0: No effect. 1: Enable Overflow Error Interrupt. • RX_BK_RDY: Received OUT Data Interrupt Enable 0: No effect. 1: Enable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0: No effect. 1: Enable Transmitted IN Data Complete Interrupt. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable 0: No effect. 1: Enable TX Packet Ready/Transaction Error Interrupt.
37.6.10 UDPHS Endpoint Control Disable Register Name: UDPHS_EPTCTLDISx [x=0..
• ERR_OVFLW: Overflow Error Interrupt Disable 0: No effect. 1: Disable Overflow Error Interrupt. • RX_BK_RDY: Received OUT Data Interrupt Disable 0: No effect. 1: Disable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0: No effect. 1: Disable Transmitted IN Data Complete Interrupt. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable 0: No effect. 1: Disable TX Packet Ready/Transaction Error Interrupt.
37.6.11 UDPHS Endpoint Control Register Name: UDPHS_EPTCTLx [x=0..
If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, ERR_FL_ISO...), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
• STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled 0: Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1: Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. • NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled 0: NAKIN Interrupt is masked. 1: NAKIN/Bank Flush Error Interrupt is enabled. • NAK_OUT: NAKOUT Interrupt Enabled 0: NAKOUT Interrupt is masked. 1: NAKOUT Interrupt is enabled.
37.6.12 UDPHS Endpoint Set Status Register Name: UDPHS_EPTSETSTAx [x=0..6] Address: 0xFFF78114 [0], 0xFFF78134 [1], 0xFFF78154 [2], 0xFFF78174 [3], 0xFFF78194 [4], 0xFFF781B4 [5], 0xFFF781D4 [6] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 TX_PK_RDY 10 – 9 KILL_BANK 8 – 7 – 6 – 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – • FRCESTALL: Stall Handshake Request Set 0: No effect.
37.6.13 UDPHS Endpoint Clear Status Register Name: UDPHS_EPTCLRSTAx [x=0..
• NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Clear 0: No effect. 1: Clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. • NAK_OUT: NAKOUT Clear 0: No effect. 1: Clear the NAK_OUT flag of UDPHS_EPTSTAx.
37.6.14 UDPHS Endpoint Status Register Name: UDPHS_EPTSTAx [x=0..
• ERR_OVFLW: Overflow Error This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
Note1: A transaction error occurs when the toggle sequencing does not respect the Universal Serial Bus Specification, Rev 2.0 (5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data....) Note2: When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT Data flag (RX_BK_RDY). If this bit is reset, then the user should consider that a new n-transaction is coming.
• CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction – Current Bank: (all endpoints except Control endpoint) These bits are set by hardware to indicate the number of the current bank. 00 Bank 0 (or single bank) 01 Bank 1 10 Bank 2 11 Invalid Note: The current bank is updated each time the user: – Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank. – Clears the received OUT data bit to access the next bank.
37.6.15 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer.
37.6.16 UDPHS DMA Next Descriptor Address Register Name: UDPHS_DMANXTDSCx [x = 1..5] Address: 0xFFF78320 [1], 0xFFF78330 [2], 0xFFF78340 [3], 0xFFF78350 [4], 0xFFF78360 [5] Access: Read/Write 31 30 29 28 27 NXT_DSC_ADD 26 25 24 23 22 21 20 19 NXT_DSC_ADD 18 17 16 15 14 13 12 11 NXT_DSC_ADD 10 9 8 7 6 5 4 3 NXT_DSC_ADD 2 1 0 • NXT_DSC_ADD This field points to the next channel descriptor to be processed.
37.6.17 UDPHS DMA Channel Address Register Name: UDPHS_DMAADDRESSx [x = 1..5] Address: 0xFFF78324 [1], 0xFFF78334 [2], 0xFFF78344 [3], 0xFFF78354 [4], 0xFFF78364 [5] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD 23 22 21 20 BUFF_ADD 15 14 13 12 BUFF_ADD 7 6 5 4 BUFF_ADD • BUFF_ADD This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary.
37.6.18 UDPHS DMA Channel Control Register Name: UDPHS_DMACONTROLx [x = 1..
• END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0: USB end of transfer is ignored. 1: UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
37.6.19 UDPHS DMA Channel Status Register Name: UDPHS_DMASTATUSx [x = 1..
• DESC_LDST: Descriptor Loaded Status 0: Cleared automatically when read by software. 1: Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
38. Image Sensor Interface (ISI) 38.1 Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller.
Figure 38-1. ISI Connection Example Image Sensor Image Sensor Interface ISI_DATA[11..0] data[11..
38.4 Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock.
Figure 38-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D 38.4.2 Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order.
Table 38-5.
38.4.4 Preview Path 38.4.4.1 Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. Table 38-6. Decimation Factor Dec value 0->15 16 17 18 19 ... 124 125 126 127 Dec Factor X 1 1.063 1.
Figure 38-5. Resize Examples 1280 32/16 decimation 640 1024 480 1280 56/16 decimation 352 1024 288 38.4.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y – Y off R G = C 0 – C 2 – C 3 × C b – C boff B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB: R = 1.
38.4.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel.
38.4.4.5 Example The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is programmed in the ISI user interface DMA_P_DSCR. To enable Descriptor fetch operation DMA_P_CTRL register must be set to 0x00000001. LLI_0 and LLI_1 are the two descriptors of the Linked list. Destination Address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR) Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL) Next FBD address: 0x00030010 (LLI_0.
38.4.5 Codec Path 38.4.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = C0 C1 C2 Cb –C6 –C7 C8 C3 –C4 –C5 Y off R × G + Cr off B Cb off An example of coefficients is given below: Y = 0.257 ⋅ R + 0.504 ⋅ G + 0.098 ⋅ B + 16 C = 0.439 ⋅ R – 0.368 ⋅ G – 0.
38.5 Image Sensor Interface (ISI) User Interface Table 38-9.
38.5.1 ISI Configuration 1 Register Name: ISI_CFG1 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 – 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 DISCR 10 9 FRATE 8 5 – 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 – 0 – THMASK • HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high. 1: HSYNC active low. • VSYNC_POL: Vertical Synchronization Polarity 0: VSYNC active high. 1: VSYNC active low.
• THMASK: Threshold Mask 0: Only 4 beats AHB burst are allowed. 1: Only 4 and 8 beats AHB burst are allowed. 2: 4, 8 and 16 beats AHB burst are allowed. • SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. • SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame.
38.5.2 ISI Configuration 2 Register Name: ISI_CFG2 Access: Read/Write 31 30 29 RGB_CFG 23 28 YCC_SWAP 22 21 20 27 - 26 25 IM_HSIZE 24 19 18 17 16 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE • IM_VSIZE: Vertical Size of the Image Sensor [0..2047] Vertical size = IM_VSIZE + 1. • GS_MODE 0: 2 pixels per word. 1: 1 pixel per word. • RGB_MODE: RGB Input Mode 0: RGB 8:8:8 24 bits. 1: RGB 5:6:5 16 bits.
• YCC_SWAP: Defines the YCC Image Data YCC_SWAP Byte 0 Byte 1 Byte 2 Byte 3 00: Default Cb(i) Y(i) Cr(i) Y(i+1) 01: Mode1 Cr(i) Y(i) Cb(i) Y(i+1) 10: Mode2 Y(i) Cb(i) Y(i+1) Cr(i) 11: Mode3 Y(i) Cr(i) Y(i+1) Cb(i) • RGB_CFG: Defines RGB Pattern when RGB_MODE is set to 1 RGB_CFG Byte 0 Byte 1 Byte 2 Byte 3 00: Default R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B 01: Mode1 B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R 10: Mode2 G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) 11: Mode3 G(LSB)/B
38.5.3 ISI Preview Register Name: ISI_PSIZE Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 19 18 17 11 – 10 – 9 3 2 1 24 PREV_HSIZE 16 PREV_HSIZE 15 – 14 – 13 – 12 – 7 6 5 4 8 PREV_VSIZE 0 PREV_VSIZE • PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode). • PREV_HSIZE: Horizontal Size for the Preview Path Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).
38.5.4 ISI Preview Decimation Factor Register Name: ISI_PDECF Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 DEC_FACTOR • DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation.
38.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register Name: ISI_Y2R_SET0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875.
38.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register Name: ISI_Y2R_SET1 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 Cboff 13 Croff 12 Yoff 11 – 10 – 9 – 8 C4 C4 • C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. • Yoff: Color Space Conversion Luminance Default Offset 0: No offset. 1: Offset = 128.
38.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register Name: ISI_R2Y_SET0 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Roff 19 18 17 16 11 10 9 8 3 2 1 0 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875.
38.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register Name: ISI_R2Y_SET1 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Goff 19 18 17 16 11 10 9 8 3 2 1 0 C5 15 14 13 12 C4 7 6 5 4 C3 • C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. • C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375.
38.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register Name: ISI_R2Y_SET2 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Boff 19 18 17 16 11 10 9 8 3 2 1 0 C8 15 14 13 12 C7 7 6 5 4 C6 • C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. • C7: Color Space Conversion Matrix Coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375.
38.5.10 ISI Control Register Name: ISI_CTRL Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 ISI_CDC 7 – 6 – 5 – 4 – 3 – 2 ISI_SRST 1 ISI_DIS 0 ISI_EN • ISI_EN: ISI Module Enable Request Write one to this field to enable the module. Software must poll ENABLE field in the ISI_STATUS register to verify that the command has successfully completed.
38.5.11 ISI Status Register Name: ISI_SR Access: Read-only 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 SIP 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 CDC_PND 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 ENABLE • ENABLE (this bit is a status bit) 0: Module is enabled. 1: Module is disabled. • DIS_DONE: Module Disable Request has Terminated 1: Disable request has completed.
• P_OVR: Preview Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. • C_OVR: Codec Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO.
38.5.
38.5.
38.5.14 ISI Interrupt Mask Register Name: ISI_IMR Access: Read/Write 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 – 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 – • DIS_DONE: Module Disable Operation Completed 0: The disable completed interrupt is disabled. 1: The disable completed interrupt is enabled.
• FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled.
38.5.15 DMA Channel Enable Register Name: DMA_CHER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_EN 0 P_CH_EN • P_CH_EN: Preview Channel Enable Write one to this field to enable the preview DMA channel. • C_CH_EN: Codec Channel Enable Write one to this field to enable the codec DMA channel.
38.5.16 DMA Channel Disable Register Name: DMA_CHDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_DIS 0 P_CH_DIS • P_CH_DIS Write one to this field to disable the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified. • C_CH_DIS Write one to this field to disabled the channel.
38.5.17 DMA Channel Status Register Name: DMA_CHSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_S 0 P_CH_S • P_CH_S: 0: indicates that the Preview DMA channel is disabled 1: indicates that the Preview DMA channel is enabled. • C_CH_S: 0: indicates that the Codec DMA channel is disabled. 1: indicates that the Codec DMA channel is enabled.
38.5.18 DMA Preview Base Address Register Name: DMA_P_ADDR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_ADDR 23 22 21 20 P_ADDR 15 14 13 12 P_ADDR 7 6 5 4 P_ADDR • P_ADDR: Preview Image Base Address. (This address is word aligned.
38.5.19 DMA Preview Control Register Name: DMA_P_CTRL Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 P_DONE 2 P_IEN 1 P_WB 0 P_FETCH • P_FETCH: Descriptor Fetch Control Field 0: Preview channel fetch operation is disabled. 1: Preview channel fetch operation is enabled. • P_WB: Descriptor Writeback Control Field 0: Preview channel writeback operation is disabled.
38.5.20 DMA Preview Descriptor Address Register Name: DMA_P_DSCR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_DSCR 23 22 21 20 P_DSCR 15 14 13 12 P_DSCR 7 6 5 4 P_DSCR • P_DSCR: Preview Descriptor Base Address (This address is word aligned.
38.5.21 DMA Codec Base Address Register Name: DMA_C_ADDR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_ADDR 23 22 21 20 C_ADDR 15 14 13 12 C_ADDR 7 6 5 4 C_ADDR • C_ADDR: Codec Image Base Address (This address is word aligned.
38.5.22 DMA Codec Control Register Name: DMA_C_CTRL Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 C_DONE 2 C_IEN 1 C_WB 0 C_FETCH • C_FETCH: Descriptor Fetch Control Field 0: Codec channel fetch operation is disabled. 1: Codec channel fetch operation is enabled. • C_WB: Descriptor Writeback Control Field 0: Codec channel writeback operation is disabled.
38.5.23 DMA Codec Descriptor Address Register Name: DMA_C_DSCR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_DSCR 23 22 21 20 C_DSCR 15 14 13 12 C_DSCR 7 6 5 4 C_DSCR • C_DSCR: Codec Descriptor Base Address (This address is word aligned.
38.5.24 ISI Write Protection Control Name: ISI_WPCR Access: Read/Write 31 30 29 28 27 WP_KEY (0x49 => “I”) 26 25 24 23 22 21 20 19 WP_KEY (0x53 => “S”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_PEN: Write Protection Enable 0: Disables the Write Protection if WP_KEY corresponds. 1: Enables the Write Protection if WP_KEY corresponds. • WP_KEY: Write Protection Key Password Should be written at value 0x495349 (ASCII code for “ISI”).
38.5.25 ISI Write Protection Status Name: ISI_WPSR Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 WP_VSRC 15 14 13 12 WP_VSRC 7 - 6 - 5 - 4 - WP_VS • WP_VS: Write Protection Violation Status Value Description 0 0 0 0 No Write Protection Violation occurred since the last read of this register (WP_SR).
39. Touchscreen ADC Controller (TSADCC) 39.1 Description The Touchscreen ADC Controller is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC).
39.
39.3 Block Diagram Figure 39-1. TSADCC Block Diagram TSADC VDDANA TSADCC Memory Controller Trigger Selection Timer Touchscreen Sequencer ADC Control Logic TSADTRG PIO PDC User Interface Peripheral Bridge APB AD1XM AD2YP AD3YM Successive Approximation Register Analog-to-Digital Converter TSADC Clock PMC .... GPAD4 Analog Multiplexer Touchscreen Switches AD0XP GPADx TSADC Interrupt TSADVREF GND GPADx: last general-purpose ADC channel defined by the number of channels 39.
39.5 Product Dependencies 39.5.1 Power Management The TSADC controller is not continuously clocked. The programmer must first enable the TSADC controller Clock in the Power Management Controller (PMC) before using the TSADC controller. However, if the application does not require TSADC controller operations, the TSADC controller clock can be stopped when not needed and be restarted later. Configuring the TSADC controller does not require the TSADC controller clock to be enabled. 39.5.
By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding TSADCC_CDR and of the LDATA field in the TSADCC_LCDR read 0. Moreover, when a PDC channel is connected to the TSADCC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers.
The field TSSHTIM defines also the time the power switches of the Touchscreen are closed when the TSADCC performs a conversion for the Touchscreen. 39.7 Touchscreen 39.7.1 Resistive Touchscreen Principles A resistive touchscreen is based on two resistive films, each one being fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. Between the two, there is a layer that acts as an insulator, but also enables contact when you press the screen.
It is possible to correct for the switch loss by performing the operation: [VYP - VXM] / [VXP - VXM]. This requires additional measurements, as shown in Figure 39-3. Figure 39-3.
39.7.3 Pressure Measurement Method The method to measure the pressure (Rp) applied to the touchscreen is based on the knowledge of the X-Panel resistance (Rxp). Three conversions (Xpos,Z1,Z2) are necessary to determine the value of Rp (Zaxis resistance).
39.7.4 Pen Detect Method When there is no contact, it is not necessary to perform conversion. However, it is important to detect a contact by keeping the power consumption as low as possible. The proposed implementation polarizes the vertical panel by closing the switch on XP and ties the horizontal panel by an embedded resistor connected to YM. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption.
39.8 Conversion Results When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and stored in the “TSADCC Channel Data Register x (x = 0..7)” of the current channel and in the “TSADCC Last Converted Data Register” . The channel EOC bit and the bit DRDY in the “TSADCC Status Register” are both set. If the PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and DRDY can trigger an interrupt.
Figure 39-6.
39.
39.10.2 Touchscreen Mode Writing TSAMOD to “Touchscreen Only Mode” automatically enables the touchscreen pins as analog inputs, and thus disables the digital function of the corresponding pins. In Touchscreen Mode, the channels 0 to 3 corresponding to the Touchscreen inputs are automatically activated and the bits CH0 to CH3 are automatically set in the “TSADCC Channel Status Register” .
If the bit PRES in “TSADCC Mode Register” is enabled, the following sequence is performed to measure both position and pressure. 1. If SLEEP is set, wake up the ADC cell and wait for the Startup Time. 2. Close the switches on the inputs XM and Yp during the Sample and Hold Time. 3. Convert Channel Xp and store the result in both TSADCC_Z1DR and TSADCC_LCDR. 4. Close the switches on the inputs XM and YP during the Sample and Hold Time. 5.
39.10.3 Interleaved Mode In the Interleaved Mode, the conversion of the touchscreen channels are made in parallel to each channel. In addition to interleaving, the analog channels 4 and 5 can be converted more often than the touchscreen channels depending on the TSFREQ field in the register TSADCC_MR. In the interleaved mode at least one ADC channel must be enabled.
For Trigger Counter at 3: 1. Close the switches on the inputs YP and YM during the Sample and Hold Time. 2. Convert Channel YM and store the result in TSADCC_CDR3. 3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. 4. Set Trigger Counter to 4. For Trigger Counter at 4: 1. Close the switches on the inputs YP and YM during the Sample and Hold Time. 2.
For Trigger Counter at 2: 1. Close the switches on the inputs XP and XM during the Sample and Hold Time. 2. Convert Channel XM and store the result in TSADCC_CDR1. 3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. 4. Set Trigger Counter to 3. For Trigger Counter at 3: 1. Close the switches on the inputs XP and XM during the Sample and Hold Time. 2.
For Trigger Counter between 8 and (2TSFREQ+1): 1. Increment Trigger Counter. 2. If Trigger Counter equals (2TSFREQ+1), then set Trigger Counter to 0. 3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. The Trigger Counter is cleared when TSAMOD is written to define the Interleaved Mode, then it simply rolls over. 39.10.
39.11 Touchscreen ADC Controller (TSADCC) User Interface Table 39-4.
39.11.1 TSADCC Control Register Name: TSADCC_CR Address: 0xFFFB0000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – START SWRST • SWRST: Software Reset 0: No effect. 1: Resets the TSADCC simulating a hardware reset. • START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion.
39.11.
• PRES: Pressure Measurement Selection 0: Disable the pressure measurement function 1: enable the pressure measurement function • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8/ADCCLK • SHTIM: Sample & Hold Time for ADC Channels Programming 0 for SHTIM gives a Sample & Hold Time equal to 1/ADCCLK.
39.11.
39.11.4 TSADCC Touchscreen Register Name: TSADCC_TSR Address: 0xFFFB000C Access: Read/Write 31 30 29 28 – – – – 25 24 23 22 21 20 19 – – – – – 18 17 16 – – – 15 14 13 12 11 10 9 8 – – – – – – – – 3 2 1 0 7 6 5 4 – – – – 27 26 TSSHTIM TSFREQ • TSFREQ: Touchscreen Frequency in Interleaved Mode Effective only if the Touchscreen Interleaved Mode is selected. Defines the Touchscreen Frequency compared to the Trigger Frequency.
39.11.5 TSADCC Channel Enable Register Name: TSADCC_CHER Address: 0xFFFB0010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel.
39.11.6 TSADCC Channel Disable Register Name: TSADCC_CHDR Address: 0xFFFB0014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel.
39.11.7 TSADCC Channel Status Register Name: TSADCC_CHSR Address: 0xFFFB0018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Status 0: Corresponding channel is disabled. 1: Corresponding channel is enabled.
39.11.
• EOCXp: End of Conversion X Position 0: The pressure measurement is disabled or the Xp conversion is not finished. 1: The pressure measurement is enabled and the Xp conversion is complete • EOCZ1: End of Conversion Z1 Measure 0: The pressure measurement is disabled or the Z1 conversion is not finished. 1: The pressure measurement is enabled and the Z1 conversion is complete • EOCZ2: End of Conversion Z2 Measure 0: The pressure measurement is disabled or the Z2 conversion is not finished.
39.11.9 TSADCC Channel Data Register x (x = 0..7) Name: TSADCC_CDR0..
39.11.
39.11.
39.11.
39.11.
39.11.
39.11.
39.11.
39.11.
39.11.18 TSADCC Write Protection Mode Register Name: TSADCC_WPMR Address: 0xFFFB00E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection of TSADCC_MR, TSADCC_TRGR and TSADCC_TSR 0: Disables the write protection if KEY value corresponds to 0x545341 (“TSA” in ASCII). 1: Enables the write protection if KEY value corresponds to 0x545341 (“TSA” in ASCII).
39.11.19 TSADCC Write Protection Status Register Name: TSADCC_WPSR Address: 0xFFFB00E8 Access: Read/Write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 OFFSET_ERR 23 22 21 20 19 OFFSET_ERR 15 14 13 12 11 OFFSET_ERR 7 6 5 4 3 2 1 0 – – – – – – – WPS • WPS: Write Protection Status 0: Write protection is disabled. 1: Write Protection is enabled. • OFFSET_ERR: Offset Error Offset where the last unauthorized access occurred.
40. DMA Controller (DMAC) 40.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
40.
40.3 DMA Controller Peripheral Connections The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals connected on APB0 (see Table 40-1). Table 40-1.
40.4 Block Diagram Figure 40-1.
40.5 Functional Description 40.5.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
Figure 40-2. DMAC Transfer Hierarchy for Non-Memory Peripheral HDMA Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer Figure 40-3.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use. ̶ ̶ ̶ Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists.
40.5.2 Memory Peripherals Figure 40-3 on page 973 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled.
40.5.4 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffers transfers.
Figure 40-5.
40.5.4.3 Programming DMAC for Multiple Buffer Transfers Table 40-2.
40.5.4.6 Suspension of Transfers Between buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if: Note: the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the channel number. The buffer complete interrupt is generated at the completion of the buffer transfer to the destination. At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if: the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.
40.5.5.1 Programming Examples 40.5.5.2 Single-buffer Transfer (Row 1) 1. Read the Channel Handler Status Register DMAC_CHSR.ENABLE Field to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register, DMAC_EBCISR. 3. Program the following channel registers: a. Write the starting source address in the DMAC_SADDRx register for channel x. b.
40.5.5.3 Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory (see Figure 40-6 on page 982) for channel x.
Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0). 15. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripheral).
Figure 40-7. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous Address of Source Layer Address of Destination Layer Buffer 2 DADDR(3) Buffer 2 Buffer 2 SADDR(3) DADDR(2) Buffer 2 Buffer 1 SADDR(2) DADDR(1) Buffer 1 SADDR(1) Buffer 0 DADDR(0) Buffer 0 SADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 40-8 on page 984.
Figure 40-8.
40.5.5.4 Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Enable register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers: a. Write the starting source address in the DMAC_SADDRx register for channel x. b.
6. The DMAC transfer proceeds as follows: a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel number) hardware sets the buffer complete interrupt when the buffer transfer has completed. It then stalls until the STALLED[n] bit of DMAC_CHSR is cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the channel number.
Figure 40-10. DMAC Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Buffer Transfer Replay mode for SADDRx, DADDRx, CTRLAx, CTRLBx Buffer Complete interrupt generated here HDMA Transfer Complete Interrupt generated here yes Is HDMA in Row1 of HDMA State Machine table? Channel Disabled by hardware no EBCIMR[x]=1? no yes Stall until STALLED is cleared by writing to KEEPON field 40.5.5.
4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
channel. You can either respond to the Buffer Complete or Chained buffer Transfer Complete interrupts, or poll for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 40-2 on page 978, the following step is performed. 19.
Figure 40-12. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address Channel Enabled by software LLI Fetch Hardware reprograms DADDRx, CTRLAx, CTRLBx, DSCRx DMA buffer transfer Writeback of control status information in LLI Reload SADDRx Buffer Complete interrupt generated here yes HDMA Transfer Complete interrupt generated here Is HDMA in Row1 of HDMA State Machine Table? Channel Disabled by hardware no 40.5.5.
– Incrementing/decrementing or fixed address for source in SRC_INCR field. – Incrementing/decrementing or fixed address for destination in DST_INCR field. e. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. f. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. g. Write the channel configuration information into the DMAC_CFGx register for channel x. ̶ i.
Figure 40-13.
Figure 40-14. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address Channel Enabled by software Buffer Transfer Replay mode for SADDRx, Contiguous mode for DADDRx CTRLAx, CTRLBx Buffer Complete interrupt generated here Buffer Transfer Complete interrupt generated here yes Is HDMA in Row1of HDMA State Machine Table? Channel Disabled by hardware no no DMA_EBCIMR[x]=1? yes Stall until STALLED field is cleared by software writing KEEPON Field 40.5.5.
Note: 4. The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively.
18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged.
Figure 40-16.
40.5.6 Disabling a Channel Prior to Transfer Completion Under normal operation, software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENABLE[n], and hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENABLE[n] register bit. The recommended way for software to disable a channel without losing data is to use the SUSPEND[n] bit in conjunction with the EMPTY[n] bit in the Channel Handler Status Register. 1.
40.6 998 DMAC Software Requirements There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. When destination peripheral is defined as the flow controller, source single transfer request are not serviced until Destination Peripheral has asserted its Last Transfer Flag.
40.7 DMA Controller (DMAC) User Interface Table 40-3.
40.7.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0xFFFFEC00 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Note: Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed. • ARB_CFG 0: Fixed priority arbiter. 1: Modified round robin arbiter.
40.7.2 DMAC Enable Register Name: DMAC_EN Address: 0xFFFFEC04 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE • ENABLE 0: DMA Controller is disabled. 1: DMA Controller is enabled.
40.7.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0xFFFFEC08 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DSREQ7 14 SSREQ7 13 DSREQ6 12 SSREQ6 11 DSREQ5 10 SSREQ5 9 DSREQ4 8 SSREQ4 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 • DSREQx Request a destination single transfer on channel i. • SSREQx Request a source single transfer on channel i.
40.7.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0xFFFFEC0C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DCREQ7 14 SCREQ7 13 DCREQ6 12 SCREQ6 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 • DCREQx Request a destination chunk transfer on channel i. • SCREQx Request a source chunk transfer on channel i.
40.7.
40.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register Name: DMAC_EBCIER Address: 0xFFFFEC18 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] Buffer Transfer Completed Interrupt Enable Register.
40.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register Name: DMAC_EBCIDR Address: 0xFFFFEC1C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] Buffer transfer completed Disable Interrupt Register.
40.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register Name: DMAC_EBCIMR Address: 0xFFFFEC20 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] 0: Buffer Transfer completed interrupt is disabled for channel i.
40.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register Name: DMAC_EBCISR Address: 0xFFFFEC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] When BTC[i] is set, Channel i buffer transfer has terminated.
40.7.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0xFFFFEC28 Access: Write-only 31 KEEP7 30 KEEP6 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENA[7:0] When set, a bit of the ENA field enables the relevant channel.
40.7.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0xFFFFEC2C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RES7 14 RES6 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 DIS7 6 DIS6 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 • DIS[7:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated.
40.7.12 DMAC Channel Handler Status Register Name: DMAC_CHSR Address: 0xFFFFEC30 Access: Read-only 31 STAL7 30 STAL6 29 STAL5 28 STAL4 27 STAL3 26 STAL2 25 STAL1 24 STAL0 23 EMPT7 22 EMPT6 21 EMPT5 20 EMPT4 19 EMPT3 18 EMPT2 17 EMPT1 16 EMPT0 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENA[7:0] A one in any position of this field indicates that the relevant channel is enabled.
40.7.13 DMAC Channel x [x = 0..7] Source Address Register Name: DMAC_SADDRx [x = 0..7] Address: 0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3], 0xFFFFECDC [4], 0xFFFFED04 [5], 0xFFFFED2C [6], 0xFFFFED54 [7] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADDRx 23 22 21 20 SADDRx 15 14 13 12 SADDRx 7 6 5 4 SADDRx • SADDRx Channel x source address. This register must be aligned with the source transfer width.
40.7.14 DMAC Channel x [x = 0..7] Destination Address Register Name: DMAC_DADDRx [x = 0..7] Address: 0xFFFFEC40 [0], 0xFFFFEC68 [1], 0xFFFFEC90 [2], 0xFFFFECB8 [3], 0xFFFFECE0 [4], 0xFFFFED08 [5], 0xFFFFED30 [6], 0xFFFFED58 [7] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DADDRx 23 22 21 20 DADDRx 15 14 13 12 DADDRx 7 6 5 4 DADDRx • DADDRx Channel x destination address. This register must be aligned with the destination transfer width.
40.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register Name: DMAC_DSCRx [x = 0..7] Address: 0xFFFFEC44 [0], 0xFFFFEC6C [1], 0xFFFFEC94 [2], 0xFFFFECBC [3], 0xFFFFECE4 [4], 0xFFFFED0[5] 0xFFFFED34 [6], 0xFFFFED5C [7] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 DSCRx 23 22 21 20 DSCRx 15 14 13 12 DSCRx 7 6 5 4 DSCRx • DSCRx_IF 00: The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0.
40.7.16 DMAC Channel x [x = 0..7] Control A Register Name: DMAC_CTRLAx [x = 0..7] Address: 0xFFFFEC48 [0], 0xFFFFEC70 [1], 0xFFFFEC98 [2], 0xFFFFECC0 [3], 0xFFFFECE8 [4], 0xFFFFED10 [5], 0xFFFFED38 [6], 0xFFFFED60 [7] Access: Read/Write 31 DONE 30 – 29 28 23 – 22 21 DCSIZE 15 14 13 27 – 26 – 25 20 19 – 18 17 SCSIZE 16 12 11 10 9 8 3 2 1 0 DST_WIDTH 24 SRC_WIDTH BTSIZE 7 6 5 4 BTSIZE • BTSIZE Buffer Transfer Size.
• DCSIZE Destination Chunk Transfer size. DCSIZE Number of data transferred 000 1 001 4 010 8 011 16 100 32 101 64 110 128 111 256 • SRC_WIDTH SRC_WIDTH Single Transfer Size 00 BYTE 01 HALF-WORD 1X WORD • DST_WIDTH DST_WIDTH Single Transfer Size 00 BYTE 01 HALF-WORD 1X WORD • DONE 0: The transfer is performed. 1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register.
40.7.17 DMAC Channel x [x = 0..7] Control B Register Name: DMAC_CTRLBx [x = 0..
• DST_DSCR 0: Destination address is updated when the descriptor is fetched from the memory. 1: Buffer Descriptor Fetch operation is disabled for the destination. • FC This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
40.7.18 DMAC Channel x [x = 0..7] Configuration Register Name: DMAC_CFGx [x = 0..
• LOCK_B 0: AHB Bus Locking capability is disabled. 1: AHB Bus Locking capability is enabled. • LOCK_IF_L 0: The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1: The Master Interface Arbiter is locked by the channel x for a buffer transfer. • AHB_PROT AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection.
40.7.19 DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register Name: DMAC_SPIPx [x = 0..
40.7.20 DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register Name: DMAC_DPIPx [x = 0..
41. Pulse Width Modulation Controller (PWM) 41.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
41.3 Block Diagram Figure 41-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Channel Period PWMx Update Duty Cycle Clock Selector Comparator PWMx Counter PIO PWM0 Channel Period PWM0 Update Duty Cycle Clock Selector PMC MCK Clock Generator Comparator Counter APB Interface Interrupt Generator APB 41.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 41-1.
41.5 Product Dependencies 41.5.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
41.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. ̶ Clocked by the system clock, MCK, the clock generator module provides 13 clocks. ̶ Each channel can independently choose one of the clock generator outputs. ̶ Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 41.6.1 PWM Clock Generator Figure 41-2.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 41.6.2 PWM Channel 41.6.2.1 Block Diagram Figure 41-3.
41.6.2.2 Waveform Properties The different properties of output waveforms are: the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
Figure 41-4. Non Overlapped Center Aligned Waveforms No overlap PWM0 PWM1 Period Note: 1. See Figure 41-5 on page 1030 for a detailed description of center aligned waveforms. When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
Figure 41-5.
41.6.3 PWM Controller Operations 41.6.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: Configuration of the clock generator if DIVA and DIVB are required Selection of the clock for each channel (CPRE field in the PWM_CMRx register) Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
Figure 41-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR according to the enabled channel(s).
41.7 Pulse Width Modulation Controller (PWM) User Interface Table 41-4.
41.7.1 PWM Mode Register Name: PWM_MR Address: 0xFFFB8000 Access: Read/Write 31 – 30 – 29 – 28 – 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 PREB DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2–255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
41.7.2 PWM Enable Register Name: PWM_ENA Address: 0xFFFB8004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Enable PWM output for channel x.
41.7.3 PWM Disable Register Name: PWM_DIS Address: 0xFFFB8008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Disable PWM output for channel x.
41.7.4 PWM Status Register Name: PWM_SR Address: 0xFFFB800C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled.
41.7.5 PWM Interrupt Enable Register Name: PWM_IER Address: 0xFFFB8010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Enable interrupt for PWM channel x.
41.7.6 PWM Interrupt Disable Register Name: PWM_IDR Address: 0xFFFB8014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Disable interrupt for PWM channel x.
41.7.7 PWM Interrupt Mask Register Name: PWM_IMR Address: 0xFFFB8018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: Interrupt for PWM channel x is disabled. 1: Interrupt for PWM channel x is enabled.
41.7.8 PWM Interrupt Status Register Name: PWM_ISR Address: 0xFFFB801C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No new channel period has been achieved since the last read of the PWM_ISR. 1: At least one new channel period has been achieved since the last read of the PWM_ISR.
41.7.9 PWM Channel Mode Register Name: PWM_CMR[0..
• CPD: Channel Update Period 0: Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1: Writing to the PWM_CUPDx will modify the period at the next period start event.
41.7.10 PWM Channel Duty Cycle Register Name: PWM_CDTY[0..3] Address: 0xFFFB8204 [0], 0xFFFB8224 [1], 0xFFFB8244 [2], 0xFFFB8264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
41.7.11 PWM Channel Period Register Name: PWM_CPRD[0..3] Address: 0xFFFB8208 [0], 0xFFFB8228 [1], 0xFFFB8248 [2], 0xFFFB8268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
41.7.12 PWM Channel Counter Register Name: PWM_CCNT[0..3] Address: 0xFFFB820C [0], 0xFFFB822C [1], 0xFFFB824C [2], 0xFFFB826C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register).
41.7.13 PWM Channel Update Register Name: PWM_CUPD[0..3] Address: 0xFFFB8210 [0], 0xFFFB8230 [1], 0xFFFB8250 [2], 0xFFFB8270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD • CUPD: Channel Update Register This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
42. AC97 Controller (AC97C) 42.1 Description The AC97 Controller is the hardware implementation of the AC97 digital controller (DC’97) compliant with AC97 Component Specification 2.2. The AC97 Controller communicates with an audio codec (AC97) or a modem codec (MC’97) via the AC-link digital serial interface. All digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the AC-link protocol.
42.3 Block Diagram Figure 42-1. Functional Block Diagram MCK Clock Domain Slot Number SYNC AC97 Slot Controller Slot Number 16/20 bits Slot #0 Transmit Shift Register M AC97 Tag Controller Receive Shift Register Slot #0,1 U AC97 CODEC Channel AC97C_COTHR AC97C_CORHR X Slot #1,2 Slot #2 SDATA_OUT Transmit Shift Register Receive Shift Register SDATA_IN AC97 Channel A Transmit Shift Register AC97C_CATHR AC97C_CARHR Slot #3...
42.4 Pin Name List Table 42-1. I/O Lines Description Pin Name Pin Description Type AC97CK 12.288-MHz bit-rate clock Input AC97RX Receiver Data (Referred as SDATA_IN in AC-link spec) Input AC97FS 48-kHz frame indicator and synchronizer Output AC97TX Transmitter Data (Referred as SDATA_OUT in AC-link spec) Output The AC97 reset signal provided to the primary codec can be generated by a PIO. 42.5 Application Block Diagram Figure 42-2.
42.6 Product Dependencies 42.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the AC97 Controller receiver, the PIO controller must be configured in order for the AC97C receiver I/O lines to be in AC97 Controller peripheral mode. Before using the AC97 Controller transmitter, the PIO controller must be configured in order for the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode. Table 42-2.
42.7 Functional Description 42.7.1 Protocol overview AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple input and output Pulse Code Modulation PCM audio streams, as well as control register accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots. Figure 42-3.
42.7.2 Slot Description 42.7.2.1 Tag Slot The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The next 12 bit positions sampled by the AC97 Controller indicate which of the corresponding 12 time slots contain valid data. The slot’s last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec.
42.7.3 AC97 Controller Channel Organization The AC97 Controller features a Codec channel and two logical channels: Channel A, Channel B. The Codec channel controls AC97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. Channel A, Channel B transfer data to/from AC97 codec. All audio samples and modem data must transit by these two channels.
42.7.3.1 AC97 Controller Setup The following operations must be performed in order to bring the AC97 Controller into an operating state: 1. Enable the AC97 Controller clock in the PMC controller. 2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (AC97C_MR). 3. Configure the input channel assignment by controlling the AC97 Controller Input Assignment Register (AC97C_ICA). 4.
In most cases, the AC97 Controller is embedded in chips that target audio player devices. In such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating system. In order to avoid these polling drawbacks, the application can perform audio streams by using PDC connected to channel A, which reduces processor overhead and increases performance especially under an operating system.
42.7.3.5 AC97 Input Frame The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used according to AC97 Controller Output Channel Assignment Register (AC97C_ICA) content.
42.7.3.10 To Transmit a10-bit Sample Stored in Big Endian Format on AC-link Halfword to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR). 31 24 23 16 – 15 – 8 7 Byte0[7:0] 0 {0x00, Byte1[1:0]} Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit). 31 24 23 16 – 15 – 10 – 9 8 Byte1 [1:0] 7 0 Byte0[7:0] Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}. 42.7.3.
42.7.4 Variable Sample Rate The problem of variable sample rate can be summarized by a simple example. When passing a 44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. The new AC97 standard approach calls for the addition of “on-demand” slot request flags.
The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously (regarding AC97FS) detected by the AC97 Controller. If WKUP bit is enabled in AC97C_IMR, an interrupt is triggered that wakes up the AC97 Controller which should then immediately issue a cold or a warm reset.
42.8 AC97 Controller (AC97C) User Interface Table 42-6.
42.8.1 AC97 Controller Mode Register Name: AC97C_MR Address: 0xFFFAC008 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 VRA • VRA: Variable Rate (for Data Slots 3-12) 0: Variable Rate is inactive. (48 kHz only) 1: Variable Rate is active. • WRST: Warm Reset 0: Warm Reset is inactive. 1: Warm Reset is active. • ENA: AC97 Controller Global Enable 0: No effect.
42.8.2 AC97 Controller Input Channel Assignment Register Name: AC97C_ICA Address: 0xFFFAC010 Access: Read/Write 31 – 23 30 – 22 CHID10 14 15 CHID8 7 6 29 21 13 CHID7 5 CHID5 28 CHID12 20 12 4 CHID4 27 26 19 CHID9 11 18 3 25 CHID11 17 24 16 CHID8 10 CHID6 2 9 1 CHID3 8 CHID5 0 • CHIDx: Channel ID for the input slot x CHIDx Selected Receive Channel 0x0 None. No data will be received during this slot time 0x1 Channel A data will be received during this slot time.
42.8.3 AC97 Controller Output Channel Assignment Register Name: AC97C_OCA Address: 0xFFFAC014 Access: Read/Write 31 – 23 30 – 22 CHID10 14 15 CHID8 7 6 29 21 13 CHID7 5 CHID5 28 CHID12 20 12 4 CHID4 27 26 19 CHID9 11 18 3 • CHIDx: Channel ID for the output slot x CHIDx 1064 Selected Transmit Channel 0x0 None. No data will be transmitted during this slot time 0x1 Channel A data will be transferred during this slot time.
42.8.4 AC97 Controller Codec Channel Receive Holding Register Name: AC97C_CORHR Address: 0xFFFAC040 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 SDATA SDATA • SDATA: Status Data Data sent by the CODEC in the third AC97 input frame slot (Slot 2).
42.8.5 AC97 Controller Codec Channel Transmit Holding Register Name: AC97C_COTHR Address: 0xFFFAC044 Access: Write-only 31 – 23 READ 15 30 – 22 29 – 21 28 – 20 14 13 12 27 – 19 CADDR 11 26 – 18 25 – 17 24 – 16 10 9 8 3 2 1 0 CDATA 7 6 5 4 CDATA • READ: Read-write Command 0: Write operation to the CODEC register indexed by the CADDR address. 1: Read operation to the CODEC register indexed by the CADDR address.
42.8.6 AC97 Controller Channel A, Channel B, Receive Holding Register Name: AC97C_CARHR, AC97C_CBRHR Address: 0xFFFAC020 Address: 0xFFFAC030 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDATA RDATA 7 6 5 4 RDATA • RDATA: Receive Data Received Data on channel x.
42.8.7 AC97 Controller Channel A, Channel B, Transmit Holding Register Name: AC97C_CATHR, AC97C_CBTHR Address: 0xFFFAC024 Address: 0xFFFAC034 Access: Write-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 TDATA TDATA 7 6 5 4 TDATA • TDATA: Transmit Data Data to be sent on channel x.
42.8.8 AC97 Controller Channel A Status Register Name: AC97C_CASR Address: 0xFFFAC028 Access: Read-only 31 – 23 – 15 RXBUFF 7 – 30 – 22 – 14 ENDRX 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 TXBUFE 3 – 26 – 18 – 10 ENDTX 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
• TXBUFE: Transmit Buffer Empty for Channel A 0: AC97C_CATCR or AC97C_CATNCR have a value other than 0. 1: Both AC97C_CATCR and AC97C_CATNCR have a value of 0. • ENDRX: End of Reception for Channel A 0: The register AC97C_CARCR has not reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. 1: The register AC97C_CARCR has reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. • RXBUFF: Receive Buffer Full for Channel A 0: AC97C_CARCR or AC97C_CARNCR have a value other than 0.
42.8.9 AC97 Controller Channel B Status Register Name: AC97C_CBSR Address: 0xFFFAC038 Access: Read-only 31 – 23 – 15 RXBUFF 7 – 30 – 22 – 14 ENDRX 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 TXBUFE 2 UNRUN 25 – 17 – 9 ENDTX 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
• TXBUFE: Transmit Buffer Empty for Channel B 0: AC97C_CBTCR or AC97C_CBTNCR have a value other than 0. 1: Both AC97C_CBTCR and AC97C_CBTNCR have a value of 0. • ENDRX: End of Reception for Channel B 0: The register AC97C_CBRCR has not reached 0 since the last write in AC97C_CBRCR or AC97C_CBRNCR. 1: The register AC97C_CBRCR has reached 0 since the last write in AC97C_CBRCR or AC97C_CBRNCR. • RXBUFF: Receive Buffer Full for Channel B 0: AC97C_CBRCR or AC97C_CBRNCR have a value other than 0.
42.8.10 AC97 Controller Codec Status Register Name: AC97C_COSR Address: 0xFFFAC048 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
42.8.
• CEM: Channel A Endian Mode 0: Transferring Data through Channel A is straight forward (Little-Endian). 1: Transferring Data through Channel A from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel A Enable 0: Data transfer is disabled on Channel A. 1: Data transfer is enabled on Channel A. • PDCEN: Peripheral Data Controller Channel Enable 0: Channel A is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated.
42.8.
• CEM: Channel B Endian Mode 0: Transferring Data through Channel B is straight forward (Little-Endian). 1: Transferring Data through Channel B from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel B Enable 0: Data transfer is disabled on Channel B. 1: Data transfer is enabled on Channel B. • PDCEN: Peripheral Data Controller Channel Enable 0: Channel B is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated.
42.8.
42.8.14 AC97 Controller Status Register Name: AC97C_SR Address: 0xFFFAC050 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF WKUP and SOF flags in AC97C_SR are automatically cleared by a processor read operation. • SOF: Start Of Frame 0: No Start of Frame has been detected since the last read of the Status Register.
42.8.15 AC97 Codec Controller Interrupt Enable Register Name: AC97C_IER Address: 0xFFFAC054 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: No effect. 1: Enables the corresponding interrupt.
42.8.16 AC97 Controller Interrupt Disable Register Name: AC97C_IDR Address: 0xFFFAC058 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: No effect. 1: Disables the corresponding interrupt.
42.8.17 AC97 Controller Interrupt Mask Register Name: AC97C_IMR Address: 0xFFFAC05C Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
43. True Random Number Generator (TRNG) 43.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. As soon as the TRNG is enabled (TRNG_CTRL register), the generator provides one 32-bit value every 84 clock cycles. Interrupt trng_int can be enabled through the TRNG_IER (respectively disabled in TRNG_IDR). This interrupt is set when a new random value is available and is cleared when the status register is read (TRNG_SR).
43.2 True Random Number Generator (TRNG) User Interface Table 43-1.
43.2.1 TRNG Control Register Name: TRNG_CR Address: 0xFFFCC000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE • ENABLE: Enables the TRNG to provide random values 0: Disables the TRNG. 1: Enables the TRNG. • KEY: Security Key KEY = 0x524e47 (RNG in ASCII). This key is to be written when the ENABLE bit is set or cleared.
43.2.2 TRNG Interrupt Enable Register Name: TRNG_IER Address: 0xFFFCC010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
43.2.3 TRNG Interrupt Disable Register Name: TRNG_IDR Address: 0xFFFCC014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
43.2.4 TRNG Interrupt Mask Register Name: TRNG_IMR Address: 0xFFFCC018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
43.2.5 TRNG Interrupt Status Register Name: TRNG_ISR Address: 0xFFFCC01C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid or TRNG is disabled. 1: New Random value is completed. DATRDY is cleared when this register is read.
43.2.6 TRNG Output Data Register Name: TRNG_ODATA Address: 0xFFFCC050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.
44. LCD Controller (LCDC) 44.1 Description The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method.
44.3 Block Diagram Figure 44-1.
44.4 I/O Lines Description Table 44-1.
Table 44-2. 44.5.
44.5.3 Interrupt Sources The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC. Table 44-3. 44.6 Peripheral IDs Instance ID LCDC 23 Functional Description The LCD Controller consists of two main blocks (Figure 44-1 on page 1092), the DMA controller and the LCD controller core (LCDC core).
Note: LINEVAL is the vertical size of the display in pixels, minus 1, as programmed in the LINEVAL field of the LCDFRMCFG register of the LCD Controller. X_size is calculated as an up-rounding of a division by 32. (This can also be done adding 31 to the dividend before using an integer division by 32).
Figure 44-2. Datapath Structure Input Interface FIFO Serializer Configuration IF Palette Control Interface Dithering Output Shifter Output Interface This module transforms the data read from the memory into a format according to the LCD module used. It has four different interfaces: the input interface, the output interface, the configuration interface and the control interface. The input interface connects the datapath with the DMA controller.
These parameters are different for the different configurations of the LCD Controller and are shown in Table 44-4. Table 44-4. Datapath Parameters Configuration DISTYPE SCAN IFWIDTH initial_latency cycles_per_data 9 1 TFT STN Mono Single 4 13 4 STN Mono Single 8 17 8 STN Mono Dual 8 17 8 STN Mono Dual 16 25 16 STN Color Single 4 11 2 STN Color Single 8 12 3 STN Color Dual 8 14 4 STN Color Dual 16 15 6 44.6.2.
Table 44-6.
Table 44-8.
For the structure of each LUT entry, see Table 44-10. Table 44-10. Lookup Table Structure in the Memory Address Data Output [15:0] 00 Red_value_0[4:0] Green_value_0[5:0] Blue_value_0[4:0] 01 Red_value_1[4:0] Green_value_1[5:0] Blue_value_1[4:0] FE Red_value_254[4:0] Green_value_254[5:0] Blue_value_254[4:0] FF Red_value_255[4:0] Green_value_255[5:0] Blue_value_255[4:0] ... In STN Monochrome, only the four most significant bits of the red value are used (16 gray shades).
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively. The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The dithering pattern for the first pair member is the inversion of the one for the second. The DP_i registers contain a series of 4-bit patterns. The (3-m)th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame.
Table 44-13.
Figure 44-3. Full Frame Timing, MMODE = 1, MVAL = 1 LCDVSYNC LCDMOD Line1 LCDDOTCK Figure 44-4. Line2 Line3 Line4 Line5 Line3 Line4 Line5 Full Frame Timing, MMODE = 0 LCDVSYNC LCDMOD LCDDOTCK Line1 Line2 The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be displayed on the panel. The following timing parameters can be configured: Vertical to Horizontal Delay (VHDLY): The delay between the falling edge of LCDVSYNC and the generation of LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to (VHDLY+1) LCDDOTCK cycles.
Figure 44-5. STN Panel Timing, CLKMOD 0 Frame Period LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD Line Period VHDLY+ HPW+1 HOZVAL+1 HBP+1 HFP+VHDLY+2 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1/2 PCLK 1/2 PCLK 1 PCLK Figure 44-6.
Figure 44-7. TFT Panel Timing (Line Expanded View), CLKMOD = 1 Line Period VHDLY+1 HPW+1 HOZVAL+1 HBP+1 HFP+VHDLY+2 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK Usually the LCD_FRM rate is about 70 Hz to 75 Hz.
44.6.2.9 Display This block is used to configure the polarity of the data and control signals. The polarity of all clock signals can be configured by LCDCON2[12:8] register setting. This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and off by software the LCD module. It is also available on the LCDPWR pin.
horizontal line. This RGB or Monochrome data is shifted to the LCD driver as consecutive bits via the parallel data lines. A TFT single scan display uses up to 24 parallel data lines to shift data to successive horizontal lines one at a time until the entire frame has been shifted and transferred. The 24 data lines are divided in three bytes that define the color shade of each color component of each pixel.
Figure 44-10.
Figure 44-11.
Figure 44-12.
Table 44-15.
44.7 Interrupts The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are: DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer. FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty. FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is full.
̶ LCDFRMCFG register: program the dimensions of the LCD module used. ̶ LCDFIFO register: To program it, use the formula in section “FIFO” on page 1098. ̶ LCDMVAL register: Its configuration depends on the LCD Module used and should be tuned to improve the image quality in the display (See “Time Generator” on page 1103.) ̶ DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules.
44.10 2D Memory Addressing The LCDC can be configured to work on a frame buffer larger than the actual screen size. By changing the values in a few registers, it is easy to move the displayed area along the frame buffer width and height. Figure 44-13.
44.11 Register Configuration Guide Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. 44.11.1 STN Mode Example STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 MHz Data rate: 320*240*70*3/8 = 2.016 MHz HOZVAL = ((3*320)/8) - 1 LINEVAL = 240 -1 CLKVAL = (60 MHz/2.
44.12 LCD Controller (LCDC) User Interface Table 44-16.
Table 44-16.
44.12.1 DMA Base Address Register 1 Name: DMABADDR1 Address: 0x00500000 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 BADDR-U 23 22 21 20 BADDR-U 15 14 13 12 BADDR-U 7 6 5 4 BADDR-U • BADDR-U Base Address for the upper panel in dual scan mode. Base Address for the complete frame in single scan mode.
44.12.2 DMA Base Address Register 2 Name: DMABADDR2 Address: 0x00500004 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BADDR-L 23 22 21 20 BADDR-L 15 14 13 12 BADDR-L 7 6 5 4 BADDR-L • BADDR-L Base Address for the lower panel in dual scan mode only.
44.12.3 DMA Frame Pointer Register 1 Name: DMAFRMPT1 Address: 0x00500008 Access: Read-only 31 – 23 – 15 30 – 22 29 – 21 14 13 7 6 5 28 – 20 27 – 19 FRMPT-U 12 11 FRMPT-U 4 3 FRMPT-U 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-U Current value of frame pointer for the upper panel in dual scan mode. Current value of frame pointer for the complete frame in single scan mode. Down count from FRMSIZE to 0.
44.12.4 DMA Frame Pointer Register 2 Name: DMAFRMPT2 Address: 0x0050000C Access: Read-only 31 – 23 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 5 4 27 – 19 FRMPT-L 11 FRMPT-L 3 FRMPT-L 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-L Current value of frame pointer for the Lower panel in dual scan mode only. Down count from FRMSIZE to 0. Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame).
44.12.5 DMA Frame Address Register 1 Name: DMAFRMADD1 Address: 0x00500010 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-U 23 22 21 20 FRMADD-U 15 14 13 12 FRMADD-U 7 6 5 4 FRMADD-U • FRMADD-U Current value of frame address for the upper panel in dual scan mode. Current value of frame address for the complete frame in single scan.
44.12.6 DMA Frame Address Register 2 Name: DMAFRMADD2 Address: 0x00500014 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-L 23 22 21 20 FRMADD-L 15 14 13 12 FRMADD-L 7 6 5 4 FRMADD-L • FRMADD-L Current value of frame address for the lower panel in single scan mode only. Note: This register is read-only and contains the current value of the last DMA transaction in the bus for the panel.
44.12.7 DMA Frame Configuration Register Name: DMAFRMCFG Address: 0x00500018 Access: Read/Write 31 – 23 – 15 30 29 28 22 21 20 14 13 12 7 6 5 4 27 BRSTLN 19 FRMSIZE 11 FRMSIZE 3 FRMSIZE 26 25 24 18 17 16 10 9 8 2 1 0 • FRMSIZE: Frame Size In single scan mode, this is the frame size in words. In dual scan mode, this is the size of each panel.
44.12.8 DMA Control Register Name: DMACON Address: 0x0050001C Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 DMA2DEN 27 – 19 – 11 – 3 DMAUPDT 26 – 18 – 10 – 2 DMABUSY 25 – 17 – 9 – 1 DMARST 24 – 16 – 8 – 0 DMAEN • DMAEN: DMA Enable 0: DMA is disabled. 1: DMA is enabled. • DMARST: DMA Reset (Write-only) 0: No effect. 1: Reset DMA module. DMA Module should be reset only when disabled and in idle state. • DMABUSY: DMA Busy 0: DMA module is idle.
44.12.9 LCD DMA 2D Addressing Register Name: DMA2DCFG Address: 0x00500020 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 27 25 24 19 – 11 26 PIXELOFF 18 – 10 20 – 12 17 – 9 16 – 8 7 6 5 4 3 2 1 0 ADDRINC ADDRINC • ADDRINC: DMA 2D Addressing Address increment When 2-D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the number of bytes that the DMA controller must jump between screen lines.
44.12.10 LCD Control Register 1 Name: LCDCON1 Address: 0x00500800 Access: Read/Write, except LINECNT: Read-only 31 30 29 28 27 26 25 24 18 CLKVAL 10 – 2 – 17 16 9 – 1 – 8 – 0 BYPASS LINECNT 23 15 7 – 22 LINECNT 14 CLKVAL 6 – 21 20 19 13 12 5 – 4 – 11 – 3 – • BYPASS: Bypass LCDDOTCK Divider 0: The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1: The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.
44.12.
• INVVD: LCDD polarity 0: Normal 1: Inverted • INVFRAME: LCDVSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVLINE: LCDHSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVCLK: LCDDOTCK polarity 0: Normal (LCDD fetched at LCDDOTCK falling edge) 1: Inverted (LCDD fetched at LCDDOTCK rising edge) • INVDVAL: LCDDEN polarity 0: Normal (active high) 1: Inverted (active low) • CLKMOD: LCDDOTCK mode 0: LCDDOTCK only active during active display period 1: LCDDOTCK always active •
44.12.12 LCD Timing Configuration Register 1 Name: LCDTIM1 Address: 0x00500808 Access: Read/Write 31 1 23 – 15 30 – 22 – 14 29 – 21 28 – 20 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VHDLY 19 VPW 13 12 VBP 7 6 5 4 VFP • VFP: Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0. • VBP: Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
44.12.13 LCD Timing Configuration Register 2 Name: LCDTIM2 Address: 0x0050080C Access: Read/Write 31 30 29 28 27 26 25 24 13 20 – 12 19 – 11 18 – 10 17 – 9 16 – 8 5 4 3 2 1 0 HFP 23 15 – 7 22 HFP 14 – 6 21 HPW HBP • HBP: Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is (HBP+1) LCDDOTCK cycles. • HPW: Horizontal synchronization pulse width Width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is (HPW+1) LCDDOTCK cycles.
44.12.
44.12.15 LCD FIFO Register Name: LCDFIFO Address: 0x00500814 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 FIFOTH FIFOTH • FIFOTH: FIFO Threshold Must be programmed with: FIFOTH (in Words) = 512 - (2 x DMA_BURST_LENGTH + 3) where: • 512 is the effective size of the FIFO in Words. It is the total FIFO memory size in single scan mode and half that size in dual scan mode.
44.12.16 LCDMOD Toggle Rate Value Register Name: LCDMVAL Access: Read/Write 31 MMODE 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 MVAL • MVAL: LCDMOD toggle rate value LCDMOD toggle rate if MMODE = 1. Toggle rate is MVAL + 1 line periods.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.25 Power Control Register Name: PWRCON Address: 0x0050083C Access: Read/Write 31 LCD_BUSY 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 GUARD_TIME 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 LCD_PWR • LCD_PWR: LCD Module Power Control 0 = lcd_pwr signal is low, other lcd_* signals are low. 0->1 = lcd_* signals activated, lcd_pwr is set high with the delay of GUARD_TIME frame periods. 1 = lcd_pwr signal is high, other lcd_* signals are active.
44.12.26 Contrast Control Register Name: CONTRAST_CTR Address: 0x00500840 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ENA 26 – 18 – 10 – 2 POL 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PS • PS This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows: PS 0 0 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK. 0 1 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/2.
44.12.27 Contrast Value Register Name: CONSTRAST_VAL Access: Read/Write 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 CVAL • CVAL PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.
44.12.35 LCD Write Protect Mode Register Name: LCD_WPMR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to0x4C4344 ("LCD" in ASCII). 1: Enables the Write Protect if WPKEY corresponds to0x4C4344 ("LCD" in ASCII).
44.12.36 LCD Write Protect Status Register Name: LCD_WPSR Address: 0x005008E8 Access: Read-only 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Enable 0: No Write Protect Violation has occurred since the last read of the LCD_WPSR. 1: A Write Protect Violation occurred since the last read of the LCD_WPSR.
45. Electrical Characteristics 45.1 Absolute Maximum Ratings Table 45-1. Absolute Maximum Ratings* Operating Temperature (Industrial)...............-40°C to + 85°C Junction Temperature..................................................125°C Storage Temperature..................................-60°C to + 150°C Voltage on Input Pins with Respect to Ground......-0.3V to VDDIO+0.3V(+ 4V max) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 45-2. DC Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Unit VDDIOP1 DC Supply Peripheral I/Os – 1.65 – 3.6 V VDDIOP2 DC Supply ISI – 1.65 – 3.6 V VDDANA DC Supply Analog – 3.0 3.3 3.6 V – 0.8 V Input Low-level Voltage VDDIO 3.0–3.6 V -0.3 VIL VDDIO 1.65–1.95 V -0.3 – 0.3 × VDDIO V 2 – Input High-level Voltage VDDIO + 0.3 V VIH 0.7 × VDDIO – VDDIO + 0.3 V IO Max, VDDIO 3.0–3.6 V – – 0.4 V CMOS (IO < 0.3 mA), VDDIO 1.65–1.
45.3 Power Consumption Typical power consumption of PLLs, Slow Clock and Main Oscillator Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock 45.3.
Table 45-4. Power Consumption by Peripheral in Active Mode Peripheral 45.4 Consumption AC97 5.3 DMA 0.2 EMAC 34.8 HSMCI 25.6 ISI 4.8 LCD 20.4 PIO Controller 2.2 PWM 3.8 SPI 4.7 SSC 6.6 Timer Counter Channels 6.9 TRNG 0.9 TSADC 0.1 TWI 1.3 UDPHS 21.7 UHPHS 53.2 USART 7.2 Unit µA/MHz Clock Characteristics 45.4.1 Processor Clock Characteristics Table 45-5.
45.5 Main Oscillator Characteristics Table 45-7.
45.5.2 XIN Clock Characteristics Table 45-9. XIN Clock Electrical Characteristics Symbol Parameter Min Max Unit 1/(tCPXIN) XIN Clock Frequency – – 50 MHz tCPXIN XIN Clock Period – 20 – ns tCHXIN XIN Clock High Half-period – 0.4 × tCPXIN 0.6 × tCPXIN ns tCLXIN XIN Clock Low Half-period – 0.4 × tCPXIN 0.6 × tCPXIN ns CIN XIN Input Capacitance – 25 pF RIN XIN Pulldown Resistor – 500 kΩ VIN XIN Voltage VDDOSC VDDOSC V 45.
45.6.1 32 kHz Crystal Characteristics Table 45-11. 32 kHz Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resistor Rs Crystal @ 32.768 kHz – 50 100 kΩ Cm Motional Capacitance Crystal @ 32.768 kHz – – 3 fF CSHUNT Shunt Capacitance Crystal @ 32.768 kHz – – 2 pF Min Max Unit 45.6.2 XIN32 Clock Characteristics Table 45-12.
The following configuration of fields PMC_PLLICPR.ICPLLA and CKGR_PLLAR.OUTA must be done for each PLLA frequency range. Table 45-15. PLLA Frequency Configuration PLL Frequency Range (MHz) PMC_PLLICPR.ICPLLA CKGR_PLLAR.OUTA 745–800 0 00 695–750 0 01 645–700 0 10 595–650 0 11 545–600 1 00 495–550 1 01 445–500 1 10 400–450 1 11 45.8.1 UTMI PLL Characteristics Table 45-16.
45.10 USB HS Characteristics 45.10.1 USB HS Electrical Characteristics Table 45-18. USB HS Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit RPUI Bus Pull-up Resistor on Upstream Port (idle bus) In LS or FS Mode – 1.
45.11 Touchscreen ADC (TSADC) Table 45-21. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency 10-bit resolution mode Startup Time Return from Idle Mode Min Typ Max Unit – – 13.2 MHz – – 40 µs 0.5 – – µs (1) Track and Hold Acquisition Time (TTH) ADC Clock = 13.2 MHz Conversion Time (TCT) ADC Clock = 13.2 MHz(1) – – 1.75 µs (1) – – 440 ksps Throughput Rate Note: ADC Clock = 13.2 MHz 1.
45.12 Core Power Supply POR Characteristics Table 45-25. Power-on Reset Characteristics Symbol Parameter Conditions Min Typ Max Unit VT+ Threshold Voltage Rising Minimum Slope of +2.0V/30ms 0.5 0.7 0.89 V VT- Threshold Voltage Falling – 0.4 0.6 0.85 V tRST Reset Time – 30 70 130 µs Table 45-26. Power-down Timing Specification Symbol Parameter Conditions tRSTPD Reset Delay at Power-Down From NRST low to the first supply turn-off Min Max Unit 0 – ms 45.
45.13.2.2 Read Timings Table 45-29. SMC Read Signals - NRD Controlled (READ_MODE = 1) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit 12.0 11.2 ns 0 0 ns 8.7 8.2 ns 0 0 ns (nrd setup + nrd pulse) × tCPMCK - 15.4 (nrd setup + nrd pulse) × tCPMCK - 15.5 ns (nrd setup + nrd pulse - ncs rd setup) × tCPMCK - 14.7 (nrd setup + nrd pulse - ncs rd setup) × tCPMCK - 14.7 ns nrd pulse × tCPMCK - 0.5 nrd pulse × tCPMCK - 0.2 ns 3.3V VDDIOM Supply Unit 15.0 14.
45.13.2.3 Write Timings Table 45-31. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0) SMC15 Data Out Valid before NWE High nwe pulse × tCPMCK - 2.9 nwe pulse × tCPMCK - 3.6 ns SMC16 NWE Pulse Width nwe pulse × tCPMCK - 0.7 nwe pulse × tCPMCK - 0.3 ns SMC17 NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25 valid before NWE low nwe setup × tCPMCK - 3.3 nwe setup × tCPMCK - 4.
Figure 45-4. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0]/A2–A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 D0–D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD Figure 45-5.
45.14 DDRSDRC Timings The DDRSDRC controller satisfies the timings of standard DDR2, LPDDR, SDR and LPSDR modules. DDR2, LPDDR and SDR timings are specified by the JEDEC standard. Supported speed grade limitations: DDR2-400 limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK/CK#) LPDDR (1.8V, 30 pF on data/control, 10 pF on CK) ̶ ta = 5.0 ns, fmax = 125 MHz ̶ ta = 6.0 ns, fmax = 110 MHz ̶ ta = 7.5 ns, fmax = 95 MHz SDR-100 (3.
45.15.1.2 Timing Conditions Timings are given assuming a capacitance load on MISO, SPCK and MOSI as defined in Table 45-33. Table 45-33. Capacitance Load for MISO, SPCK and MOSI (product dependent) Corner Supply Max Min 3.3V 40 pF 5 pF 1.8V 20 pF 5 pF 45.15.1.3 Timing Extraction In Figure 45-7 “SPI Master Mode 1 and 2” and Figure 45-8 “SPI Master Mode 0 and 3”, the MOSI line shifting edge is represented with a hold time = 0.
Figure 45-8. SPI Master Mode 0 and 3 SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 45-9. SPI Slave Mode 0 and 3) NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 45-10.
Figure 45-11. SPI Slave Mode - NPCS Timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI13 SPI9 SPCK (CPOL = 1) SPI16 MISO Table 45-34. 1174 SPI Timings with 3.3V Peripheral Supply Symbol Parameter SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 MISO Hold time after SPCK rises SPI2 SPCK rising to MOSI SPI3 MISO Setup time before SPCK falls SPI4 Min Max Unit – 66 MHz 14.6 – ns 0 – ns 0 0.2 ns 14.
Table 45-35. SPI Timings with 1.8V Peripheral Supply Symbol Parameter Conditions Min Max Unit SPISPCK SPI Clock – 66 MHz SPI0 MISO Setup time before SPCK rises 18.0 – ns SPI1 MISO Hold time after SPCK rises 0 – ns SPI2 SPCK rising to MOSI 0 0.2 ns SPI3 MISO Setup time before SPCK falls 17.6 – ns SPI4 MISO Hold time after SPCK falls 0 – ns SPI5 SPCK falling to MOSI 0 0.7 ns SPI6 SPCK falling to MISO 6.0 18.9 ns SPI7 MOSI Setup time before SPCK rises 0.
45.15.2 SSC 45.15.2.1 Timing Conditions Timings are given assuming a capacitance load as defined in Table 45-36. Table 45-36. Capacitance Load Corner Supply Max Min 3.3V 30 pF 0 pF 1.8V 20 pF 0 pF 45.15.2.2 Timing Extraction Figure 45-13. SSC Transmitter, TK and TF in Output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 45-14.
Figure 45-15. SSC Transmitter, TK in Output and TF in Input TK (CKI=0) TK (CKI=1) SSC2 SSC3 TF SSC4 TD Figure 45-16. SSC Receiver, RK and RF in Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 45-17. SSC Receiver, RK in Input and RF in Output RK (CKI=1) RK (CKI=0) SSC8 SSC9 RD SSC10 RF Figure 45-18.
Figure 45-19. SSC Receiver, RK in Output and RF in Input RK (CKI=0) RK (CKI=1) SSC11 SSC12 RF/RD Table 45-37. SSC Timings with 3.3V Peripheral Supply Symbol Parameter Conditions Min Max Unit 0 (1) 4.0 (1) ns Transmitter SSC0 TK edge to TF/TD (TK output, TF output) – (1) (1) SSC1 TK edge to TF/TD (TK input, TF output) – SSC2 TF setup time before TK edge (TK output) – 14.3 - tCPMCK – ns SSC3 TF hold time after TK edge (TK output) – tCPMCK - 3.9 – ns 3.7 (1) – -2.
Table 45-38. SSC Timings with 1.8V Peripheral Supply Symbol Parameter Conditions Min Max Unit Transmitter SSC0 TK edge to TF/TD (TK output, TF output) – 0(1) 4.2 (1) ns SSC1 TK edge to TF/TD (TK input, TF output) – 4.8 (1) 18.4 (1) ns SSC2 TF setup time before TK edge (TK output) – 18.4 - tCPMCK – ns SSC3 TF hold time after TK edge (TK output) – tCPMCK - 5.1 – ns (1) – -2.
45.15.3 ISI 45.15.3.1 Timing Conditions Timings are given assuming capacitance loads as defined in Table 45-39. Table 45-39. Capacitance Load Corner Supply Max Min 3.3V 30 pF 0 pF 1.8V 20 pF 0 pF 45.15.3.2 Timing Extraction Figure 45-21. ISI Timing Diagram PIXCLK ISI3 DATA[7:0] VSYNC HSYNC Table 45-40. Valid Data ISI1 Valid Data Valid Data ISI2 ISI Timings with 3.3V Peripheral Supply Symbol Parameter Min Max Unit ISI1 DATA/VSYNC/HSYNC setup time 1.
45.15.5 EMAC 45.15.5.1 Timing Conditions Timings are given assuming a capacitance load on data and clock as defined in Table 45-42. Table 45-42. Capacitance Load on Data, Clock Pads Corner Supply Max Min 3.3V 20 pF 0 pF 1.8V 20 pF 0 pF 45.15.5.2 Timing Constraints The Ethernet controller satisfies the timings of the standards given in Table 45-43, Table 45-44 and Table 45-45. Table 45-43.
Table 45-44. EMAC MII Specific Signals (Continued) Symbol Parameter Min Max Unit EMAC13 Setup for ERXER from ERXCK 10 – ns EMAC14 Hold for ERXER from ERXCK 10 – ns EMAC15 Setup for ERXDV from ERXCK 10 – ns EMAC16 Hold for ERXDV from ERXCK 10 – ns Figure 45-23.
45.15.5.4 RMII Mode Table 45-45. RMII Mode Symbol Parameter Min Max Unit EMAC21 ETXEN toggling from EREFCK rising 2 16 ns EMAC22 ETX toggling from EREFCK rising 2 16 ns EMAC23 Setup for ERX from EREFCK rising 4 ns EMAC24 Hold for ERX from EREFCK rising 2 ns EMAC25 Setup for ERXER from EREFCK rising 4 ns EMAC26 Hold for ERXER from EREFCK rising 2 ns EMAC27 Setup for ECRSDV from EREFCK rising 4 ns Figure 45-24.
45.15.6.2 Timing Extraction Figure 45-25. USART SPI Master Mode NPCSx SPI5 SPI3 CPOL = 1 SPI0 SPCK = 0 CPOL = 0 SPI4 MISO SPI4 SPI1 SPI2 LSB MSB MOSI Figure 45-26. USART SPI Slave Mode NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 45-27.
Table 45-47. USART SPI Timings with 3.3V Peripheral Supply Symbol Parameter SPI0 SPCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Min Max Unit – – ns 17.2 – ns 0 – ns – 3.5 ns Output Data Setup Time – 0.2 ns SPI5 Serial Clock to Chip Select Inactive – -0.3 ns SPI6 SPCK falling to MISO 13.8 (1) 16.9 (1) ns SPI7 MOSI Setup time before SPCK rises 7.5 – ns SPI8 MOSI Hold time after SPCK rises 2.
Table 45-48. USART SPI Timings with 1.8V Peripheral Supply Symbol Parameter SPI0 SPCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 SPI5 Min Max Unit – – ns 20.6 – ns 0 – ns – 6.0 ns Output Data Setup Time – 0.
46. Mechanical Characteristics 46.1 Package Drawings Figure 46-1.
Table 46-1. Package Information Ball Land 0.375 mm +/- 0.05 Soldering Mask Opening 0.275 mm +/- 0.03 Solder Mask Definition Solder Mask Defined Table 46-2. Device and 324-ball TFBGA Package Maximum Weight 400 mg Table 46-3. 324-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 46-4. 3 Package Reference JEDEC Drawing Reference MO-210 JESD97 Classification e1 This package respects the recommendations of the NEMI User Group. 46.
47. Marking All devices are marked with the Atmel logo and the ordering code.
48. Ordering Information Table 48-1.
49. Errata 49.1 SAM9G45 Errata - Rev. A Parts 49.1.1 Boot ROM 49.1.1.1 Boot ROM: NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free.
49.1.3 Ethernet MAC 10/100 (EMAC) 49.1.3.1 EMAC: Setup Timing Violation in RMII Mode A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V] and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V]. Problem Fix/Workaround None 49.1.4 Pulse Width Modulation Controller (PWM) 49.1.4.1 PWM: Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register.
Problem Fix/Workaround Transmit STTDLY must be different from 0. 49.1.7.2 SSC: Unexpected delay on TD output When SSC is configured with the following conditions: TCMR.STTDLY more than 0 RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge RFMR.FSOS = None (input) TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None 49.1.8 Touchscreen (TSADCC) 49.1.8.
49.1.10 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) 49.1.10.1 UHPHS/UDPHS: USB Does Not Start after Power-up The USB may not start properly at first use after power-up. Booting out of the internal ROM fixes this issue because the workaround below is applied in the ROM Code. Problem Fix/Workaround There are two possible workarounds: 1. Apply a hardware reset (NRST) after power-up or: 2. Activate the PLLUTMI twice, following the procedure below: a.
In the USB device driver, the generate_pulse_bias function must be implemented in the “USB end of reset” and “USB end of resume” interrupts.
49.2 SAM9G45 Errata - Rev. B Parts 49.2.1 Boot ROM 49.2.1.1 Boot ROM: NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free.
49.2.3 Ethernet MAC 10/100 (EMAC) 49.2.3.1 EMAC: Setup Timing Violation in RMII Mode A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V] and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V]. Problem Fix/Workaround None 49.2.4 Pulse Width Modulation Controller PWM) 49.2.4.1 PWM: Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register.
Problem Fix/Workaround Transmit STTDLY must be different from 0. 49.2.7.2 SSC: Unexpected delay on TD output When SSC is configured with the following conditions: TCMR.STTDLY more than 0 RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge RFMR.FSOS = None (input) TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None 49.2.8 Touchscreen (TSADCC) 49.2.8.
49.2.9 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) 49.2.9.1 UHPHS/UDPHS: USB Does Not Start after Power-up The USB may not start properly at first use after power-up. Booting out of the internal ROM fixes this issue because the workaround below is applied in the ROM Code. Problem Fix/Workaround There are two possible workarounds: 1. Apply a hardware reset (NRST) after power-up or: 2. Activate the PLLUTMI twice, following the procedure below: a.
The function below can be used to generate the pulse on the bias signal. void generate_pulse_bias(void) { unsigned int * pckgr_uckr = (unsigned int *) 0xFFFFFC1C; * pckgr_uckr &= ~AT91_PMC_BIASEN; * pckgr_uckr |= AT91_PMC_BIASEN; } In the USB device driver, the generate_pulse_bias function must be implemented in the “USB end of reset” and “USB end of resume” interrupts.
49.3 SAM9G45 Errata - Rev. C Parts 49.3.1 Boot ROM 49.3.1.1 Boot ROM: NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free.
49.3.3 Ethernet MAC 10/100 (EMAC) 49.3.3.1 EMAC: Setup Timing Violation in RMII Mode A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V] and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V]. Problem Fix/Workaround None 49.3.4 Pulse Width Modulation Controller PWM) 49.3.4.1 PWM: Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register.
49.3.7 Serial Synchronous Controller (SSC) 49.3.7.1 SSC: Data sent without any frame synchro When SSC is configured with the following conditions: RF is in input, TD is synchronized on a receive START (any condition: START field = 2 to 7) TF toggles at each start of data transfer Transmit STTDLY = 0 Check TD and TF after a receive START, The data is sent but there is not any toggle of the TF line Problem Fix/Workaround Transmit STTDLY must be different from 0. 49.3.7.
49.3.9 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) 49.3.9.1 UHPHS/UDPHS: USB Does Not Start after Power-up The USB may not start properly at first use after power-up. Booting out of the internal ROM fixes this issue because the workaround below is applied in the ROM Code. Problem Fix/Workaround There are two possible workarounds: 1. Apply a hardware reset (NRST) after power-up or: 2. Activate the PLLUTMI twice, following the procedure below: a.
50. Revision History In the tables that follow, the most recent version appears first. Table 50-1. SAM9G45 Datasheet Rev. 6438O Revision History Date Changes Minor formatting and editorial changes throughout Section 13. “Real-time Clock (RTC)” Table 13-1 “Register Mapping”: defined offset 0xFC as “Reserved” Section 27. “Debug Unit (DBGU)” Table 27-3 “Register Mapping”: defined offset range 0x004C–0x00FC as “Reserved” Section 28. “Serial Peripheral Interface (SPI)” Section 28.
Table 50-2. SAM9G45 Datasheet Rev. 6438N Revision History Date Changes General formatting and editorial changes throughout Updated “Description” “Features” Updated descriptions under “Peripherals”, “System”, and “Package”; added “Cryptography” Section 1. “Block Diagram” Figure 1-1 “SAM9G45 Block Diagram”: added label “Backup Section” Section 2.
Table 50-2. SAM9G45 Datasheet Rev. 6438N Revision History (Continued) Date Changes Section 21. “DDR SDR SDRAM Controller (DDRSDRC)” Section 21.4.2 “Low-power DDR1-SDRAM Initialization”: step 8 split into step 8 and new step 9; replaced step 12 with standard text Figure 21-12 “Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Device”: in diagram, inserted additional cycle (“Latency = 2” corrected to “Latency = 3”) Section 22.
Table 50-2. SAM9G45 Datasheet Rev. 6438N Revision History (Continued) Date Changes Section 35. “High Speed Multimedia Card Interface (HSMCI)” (cont’d) Section 35.14.3 “HSMCI Data Timeout Register”: added sentence about disabling write protection; updated field descriptions Section 35.14.4 “HSMCI SDCard/SDIO Register”: added sentence about disabling write protection; updated field descriptions Section 35.14.6 “HSMCI Command Register”: updated field descriptions Section 35.14.
Table 50-2. SAM9G45 Datasheet Rev. 6438N Revision History (Continued) Date Changes Section 45. “Electrical Characteristics” (cont’d) Section 45.15.1.3 “Timing Extraction”: added content relative to MISO and MOSI sampling; inserted Figure 45-6 “MISO Capture in Master Mode” Section 45.15.5.2 “Timing Constraints”: updated first sentence Table 45-45 “RMII Mode”: below table, deleted note “See Note (1) of Table 45-43.” Section 45.15.
Doc. Rev 6438J Comments Introduction: Section “Features”, added “Write Protected Registers” to the peripherals list. Section 3. “Signal Description”, added a comment to the NRST line in Table 3-1, “Signal Description List”. Change Request Ref. 8213 8350 Boot strategies: Table 11-1, “External Clock and Crystal Frequencies allowed for Boot Sequence (in MHz)” added in Section 11.3.2 “Initialization Sequence”. RSTC: Section 12.2 “Embedded Characteristics”, added a phrase about NRST.
Doc. Rev 6438J Change Request Ref. Comments (Continued) Errata: Added Section 49.1.10.2 “UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL”. 8372 Added an introduction phrase about “SAM9G45 Errata - Revision B Parts” in Section 49.1.10 “USB High Speed Host Port (UHPHS) and Device Port (UDPHS)” and a reference to this section in Section 49.2.9 “USB High Speed Host Port (UHPHS) and Device Port (UDPHS)” (new section added). rfo(1) Added Section 49.2.9.
Doc. Rev 6438H Comments (Continued) Change Request Ref. Errata: “Marking” moved from the Errata section to “SAM9G45 Mechanical Characteristics” .section. Section 49.2 “SAM9G45 Errata - Rev. B Parts” added, similar to Rev. A Parts, but without UHPHS: Packet Loss Issue in the UTMI Transceivers. Second sentence edited in “UHPHS/UDPHS: USB does not start after power-up” (Section 49.1.10.1 and Section 49.2.8.1 ). 7979 7981 EMAC Errata added to Errata MRL A and B, as Section 49.1.
Doc. Rev 6438G Change Request Ref. Comments (Continued) TWI: Section 31.2 “Embedded Characteristics”, removed reference to PDC. 7384 TRNG: Section 44.2.1 “TRNG Control Register”, added KEY bitfield. 7531 UDPHS: Figure 38-3 “Board Schematic”, GND changed to GNDUTMI. 7332 UHPHS: Figure 37-4 “Board Schematic to Interface UHP High-speed Device Controller”, GND changed to GNDUTMI 7332 Electrical Characteristics: Table 46-23, “Analog Inputs”, updated Parameter: Input “Source” impedence.
Doc. Rev 6438F Comments (Continued) Change Request Ref. Errata - “Boot ROM” errata added. 7148 - “Static Memory Controller (SMC)” errata added. 6977 - “Touch Screen (TSADCC)” errata added. 7165 - “USB High Speed Host Port (UHPHS)” errata added.
Doc. Rev 6438E Change Request Ref. Comments (Continued) DDR/SDR SDRAM Controller (DDRSDRC): “NO_OPTI” bit removed. 6871 “DIS_ANTICIP_READ” description edited. Electrical Characteristics: Section 46.14 “DDRSDRC Timings”, list of Supported speed grade limitations updated. 6776 Section 46.11 “Touch Screen ADC (TSADC)”, TTH (ns) formula edited. 6800 Last sentence in the Note added. rfo(1) SPI Master Mode figure titles reversed between Figure 46-5 and Figure 46-6.
Doc. Rev 6438D Comments (Continued) Change Request Ref. Boot strategies: Section 11.4.3.1 “NAND Flash Boot”, and Table 11-4, CS0 changed into CS3. 6682 Section 11.4.3.4 “TWI EEPROM Boot” and Table 11-4, TWI, TWD and TWCK changed into TWI0, TWD0 and TWCK0. DDR/SDR SDRAM Controller (DDRSDRC): Watermarks removed from Section 22. “DDR/SDR SDRAM Controller (DDRSDRC)”. rfo(1) Electrical Characteristics: A “Core Power Supply POR Characteristics” section has been added at the end of Section 46.
Doc. Rev 6438D Change Request Ref. Comments (Continued) USB Host Port: Section 37. “USB High Speed Host Port (UHPHS)” , HS (High Speed) was added to the title. Doc. Rev 6438C 6644 Change Request Ref. Comments Introduction: Section 3. “Signal Description” , Table 3-1, in “Reset/Test” description, NRST pin updated with note concerning NRST configuration. 6600 Section 4. “Package and Pinout”, Table 4-1 updated. 6639 Boot Program: Section 11.5.2.1 “Supported External Crystal/External Clocks”, ...
Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10. Boot Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 10.2 10.3 10.4 10.5 Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Initialization . . . . . . . . . .
17. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 17.1 17.2 17.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 General Purpose Backup Registers (GPBR) User Interface . . . . . . . . . . . . . . . .
22.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word . . . . . . . . . . . . 299 23. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 23.1 23.2 23.3 23.4 23.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . .
33.5 33.6 33.7 33.8 33.9 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 SSC Application Examples . . . . . . . . . . . . . .
39. Touchscreen ADC Controller (TSADCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 39.9 39.10 39.11 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . .
44.7 44.8 44.9 44.10 44.11 44.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-buffer Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2D Memory Addressing. . . . . . . . . . . . . . . . . . . . .
ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd.
