Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 99
SAM9G20
15. Periodic Interval Timer (PIT)
15.1 Overview
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and effi-
cient management, even for systems with long response time.
15.2 Block Diagram
Figure 15-1: Periodic Interval Timer
15.3 Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and
a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the
Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is
reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since
the last read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters
CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer
interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR (disabled on reset). The PITEN bit only becomes effective when the
CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN = 0), the CPIV goes on counting until the
PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.
20-bit
Counter
MCK/16
PIV
PIT_MR
CPIV
PIT_PIVR
PICNT
12-bit
Adder
0
0
read PIT_PIVR
CPIV PICNT
PIT_PIIR
PITS
PIT_SR
set
reset
PITIEN
PIT_MR
pit_irq
1
0
10
MCK
Prescaler
= ?