Datasheet

SAM9G20
DS60001516A-page 92  2017 Microchip Technology Inc.
14. Real-time Timer (RTT)
14.1 Overview
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers
an alarm on a programmed value.
14.2 Block Diagram
Figure 14-1: Real-time Timer
14.3 Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable
16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32768 Hz).
The 32-bit counter can count up to 2
32
seconds, corresponding to more than 136 years, then roll over to 0.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES
to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow
Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading
RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled
when the status register is clear.
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be
updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the
returned value.
The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter
value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF,
after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt,
the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
SLCK
RTPRES
RTTINC
ALMS
16-bit
Divider
32-bit
Counter
ALMV
=
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST