Datasheet

SAM9G20
DS60001516A-page 90  2017 Microchip Technology Inc.
13.4.2 Reset Controller Status Register
Name:RSTC_SR
Access:Read-only
URSTS: User Reset Status
0: No high-to-low edge on NRST happened since the last read of RSTC_SR.
1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
SRCMP: Software Reset Command in Progress
0: No software command is being performed by the reset controller. The reset controller is ready for a software command.
1: A software reset command is being performed by the reset controller. The reset controller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––SRCMPNRSTL
15 14 13 12 11 10 9 8
––––– RSTTYP
76543210
–––––––URSTS
RSTTYP Reset Type Comments
0 0 0 General Reset Both VDDCORE and VDDBU rising
0 0 1 Wake Up Reset VDDCORE rising
0 1 0 Watchdog Reset Watchdog fault occurred
0 1 1 Software Reset Processor reset required by the software
1 0 0 User Reset NRST pin detected low