Datasheet

SAM9G20
DS60001516A-page 86  2017 Microchip Technology Inc.
Figure 13-8: Watchdog Reset
13.3.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descending order:
• Backup Reset
• Wake-up Reset
• Watchdog Reset
• Software Reset
• User Reset
Particular cases are listed below:
• When in User Reset:
- A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
- A software reset is impossible, since the processor reset is being activated.
• When in Software Reset:
- A watchdog event has priority over the current state.
- The NRST has no effect.
• When in Watchdog Reset:
- The processor reset is active and so a Software Reset cannot be programmed.
- A User Reset cannot be entered.
13.3.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be per-
formed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR. This transition is also detected on the
Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by
the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit
and clears the interrupt.
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP
Any XXX
0x2 = Watchdog Reset