Datasheet

SAM9G20
DS60001516A-page 82  2017 Microchip Technology Inc.
Figure 13-4: General Reset State
13.3.4.2 Wake-up Reset
The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted
except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then
re-enabled during 3 Slow Clock cycles, depending on the requirements of the Arm processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset.
The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of
cycles is applicable.
When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the
Main Supply POR.
SLCK
periph_nreset
proc_nreset
Backup Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
Startup Time
MCK
Processor Startup
= 3 cycles
backup_nreset
Any
Freq.
RSTTYP
XXX 0x0 = General Reset
XXX
Main Supply
POR output
BMS Sampling