Datasheet

SAM9G20
DS60001516A-page 80  2017 Microchip Technology Inc.
13.3.2 NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows
the block diagram of the NRST Manager.
Figure 13-2: NRST Manager
13.3.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset
State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0
in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the
bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in
RSTC_MR must be written at 1.
13.3.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by
the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named
EXTERNAL_RESET_LENGTH, lasts 2
(ERSTL+1)
Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs
and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time
compliant with potential external devices connected on the system reset.
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a
longer startup time than the Slow Clock Oscillator.
13.3.3 BMS Sampling
The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow
clock cycles after the Core Power-On-Reset output rising edge.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset