Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 793
SAM9G20
Note 1: “rfo” indicates changes requested during document review and approval loop.
41.11.2 “SPI” Timings: The titles of the figures listed below have been updated.
Figure 41-7. “SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL =1 and NCPHA = 0)”
Figure 41-8. “SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL and NCPHA = 1)”
Figure 41-9. “SPI Slave Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)”
Figure 41-10. “SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)”
5592
Table 41-4, “Power Consumption by Peripheral in Active Mode” updatedvalues in Consumption column.
Table 41-15, “PLLA Characteristics” I
PLL
active mode, current consumption is 8 mA.
5771
Table 41-3, “Power Consumption for Different Modes” Active mode, “all peripheral clocks de-activated”. 5802
Errata:
Section 44.2.9 “Static Memory Controller (SMC)”, added to datasheet with the errata listed below:
Section 44.2.9.1 “SMC: Chip Select Parameters Modification”
5642
Doc. Rev Comments
Change
Request
Ref.
6384A First issue
Doc. Rev
6384B Comments (Continued)
Change
Request
Ref.