Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 79
SAM9G20
13. Reset Controller (RSTC)
13.1 Overview
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It
reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.
13.2 Block Diagram
Figure 13-1: Reset Controller Block Diagram
13.3 Functional Description
13.3.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates
the following reset signals:
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• backup_nreset: Affects all the peripherals powered by VDDBU.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager con-
trols the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum
value that can be found in Section 40.5 Crystal Oscillator Characteristics.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its
configuration is saved as long as VDDBU is on.
NRST
Startup
Counter
proc_nreset
wd_fault
periph_nreset
backup_neset
SLCK
Reset
State
Manager
Reset Controller
rstc_irq
NRST
Manager
exter_nreset
nrst_out
Main Supply
POR
WDRPROC
user_reset
Backup Supply
POR