Datasheet

SAM9G20
DS60001516A-page 784  2017 Microchip Technology Inc.
44.2.7.3 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro
with a Start Delay equal to zero.
Problem Fix/Workaround
None.
44.2.7.4 SSC: Periodic Transmission Limitations in Master Mode
If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
44.2.8 Shutdown Controller (SHDWC)
44.2.8.1 SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on
If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be driven to low level voltage after a delay.This
delay is linked to the startup time of the slow clock selected by OSCSEL signal.
If SHDN pin is connected to the Enable pin (EN) of the VDDCORE regulator, VDDCORE establishment does not occur and the system
does not start.
Problem Fix/Workaround
1. VDDCORE must be established within the delay corresponding to the startup time of the slow clock selected by OSCSEL.
2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output (EN_REG) can be connected to a PIO
and used to enter the shutdown mode.
44.2.9 Static Memory Controller (SMC)
44.2.9.1 SMC: Chip Select Parameters Modification
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed
on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory connected on this CS0, may
lead to unpredictable behavior.
Problem Fix/Workaround
The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to
another Chip Select
44.2.10 System Controller (SYSC)
44.2.10.1 SYSC: Possible Event Loss when reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the corresponding bit might be
cleared. This can lead to the loss of this event.
Problem Fix/Workaround
The software must handle an RTT event as an interrupt and should not poll RTT_SR.
44.2.11 Two-wire Interface (TWI)
44.2.11.1 TWI: RXRDY Flag is not reset by a SOFTWARE Reset
The RXRDY Flag is not reset when a Software reset is performed.
Problem Fix/Workaround
After a Software Reset, the Register TWI_RHR must be read.