Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 783
SAM9G20
;perform power down command
STR r1, [r0]
;perform proc_reset and periph_reset (in the ARM pipeline)
STR r3, [r2]
END
44.2.6 Serial Peripheral Interface (SPI)
44.2.6.1 SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
If the SPI is used in the following configuration:
• master mode
• CPOL = 1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system
clock frequency) and the other transfers set with SCBR not equal to 1
• transmit with the slowest chip select and then with the fastest one
then an additional pulse will be generated on output PSCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from
1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
44.2.6.2 SPI: Baudrate set to 1
When Baudrate is set to 1 (i.e., when serial clock frequency equals the system clock frequency), and when the fields BITS (number of bits
to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No error occurs if
BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
44.2.7 Serial Synchronous Controller (SSC)
44.2.7.1 SSC: Unexpected RK clock cycle when RK outputs a clock during data transfer
When the SSC receiver is used in the following configuration:
• the internal clock divider is used (CKS = 0 and DIV different from 0),
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an unexpected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
44.2.7.2 SSC: Incorrect first RK clock cycle when RK outputs a clock during data transfer
When the SSC receiver is used in the following configuration:
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of MCK/(2 x DIV).
Problem Fix/Workaround
None.