Datasheet
2017 Microchip Technology Inc. DS60001516A-page 781
SAM9G20
44.2.3.3 ECC: Unsupported hardware ECC on 16-bit NAND Flash
Hardware ECC on 16-bit NAND Flash is not supported.
Problem Fix/Workaround
Perform the ECC by software.
44.2.4 MCI
44.2.4.1 MCI: Busy Signal of R1b responses is not taken in account
The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56.
Additionally, for commands CMD42 and CMD56 a conflict can occur on data line0 if the MCI sends data to the card while the card is still
busy.The behavior is correct for CMD12 command (STOP_TRANSFER).
Problem Fix/Workaround
None.
44.2.4.2 MCI: SDIO Interrupt does not work with slots other than A
If there is 1-bit data bus width on slots other than slot A, the SDIO interrupt can not be captured. Th sample is made on the wrong data line.
Problem Fix/Workaround
None
44.2.4.3 MCI: Data Timeout Error Flag
As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled waiting indefinitely the Data start bit.
Problem Fix/Workaround
A STOP command must be sent with a software timeout.
44.2.4.4 MCI: Data Write Operation and number of bytes
The Data Write operation with a number of bytes less than 12 is impossible.
Problem Fix/Workaround
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify
the real count number.
44.2.4.5 MCI: Flag Reset is not correct in half duplex mode
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect. These flags are reset correctly after
a PDC channel enable.
Problem Fix/Workaround
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the PDC channel by writing PDC_TXTEN or
PDC_RXTEN.
44.2.5 Reset Controller (RSTC)
44.2.5.1 RSTC: Reset During SDRAM Accesses
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while data are ready to be read on the data bus.
The SDRAM maintains the data until the clock restarts.
If the user Reset is programmed to assert a general reset, the data maintained by the SDRAM leads to a data bus conflict and adversely
affects the boot memories connected on the EBI:
• NAND Flash boot functionality, if the system boots out of internal ROM.
• NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.